P520-05OC PLL [PhaseLink Corporation], P520-05OC Datasheet - Page 2

• Manufacturer Part Number: P520-05OC
• Description: Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal)
• Manufacturer: PLL [PhaseLink Corporation]

PIN DESCRIPTIONS
* Note: PLL520-06 only available in 3x3mm QFN, PLL520-07 only available in TSSOP.
** Note: DRIVSEL on pin 12 on PLL520-06 only.
FREQUENCY SELECTION TABLE
Note *: SEL3 is not available (always “1”) in 3x3mm package
All pins have internal pull-ups (default value is 1). Connect to GND to set to 0.
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 09/20/04 Page 2
DRIVSEL**
Name
VCON
XOUT
CLKC
CLKT
SEL0
SEL1
SEL2
SEL3
GND
VDD
XIN
SEL3*
OE
0*
1*
1*
1*
Pin number
Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal)
8,9, 10, 14
TSSOP*
1, 12
11
13
16
15
2
3
6
7
5
4
-
SEL2
0
0
1
1
3x3mm QFN*
Pin number
Not available
2,3,4,8,12
6,11
13
14
16
12
10
15
1
5
7
9
SEL1
1
1
1
1
Type
O
O
P
P
I
I
I
I
I
I
I
I
I
PLL520-05/-06/-07/-08/-09
Crystal in connector.
Crystal out connector.
Output enable pin.
Frequency control input (0.3V to 3.0V)
Ground (except pin 12 on PLL520-06: DRIVSEL see below).
PLL520-06 only: Drive Select Input. This pin has an internal
pull-up that will default DRIVSEL to ‘1’ when not connect to
GND. CMOS output of PLL520-06 will be high drive CMOS
when DRIVSEL is set to ‘0’, and will be standard CMOS
otherwise.
True output PECL (PLL520-08) or LVDS (PLL520-09)
(N/C for PLL520-07)
Complementary output PECL (PLL520-08) or LVDS
(PLL520-09)
(CMOS out for PLL520-07).
Multiplier selector pins. These pins have an internal pull-up
that will default SEL to ‘1’ when not connected to GND.
+3.3V power supply.
SEL0
1
1
0
1
Fin x 8 (PLL520-09 in TSSOP only)
Description
Selected Multiplier
No multiplication
Fin x 4
Fin x 2