P520-88OC PLL [PhaseLink Corporation], P520-88OC Datasheet

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P520-88OC

Manufacturer Part Number
P520-88OC
Description
Low Phase Noise VCXO (9.5-65MHz)
Manufacturer
PLL [PhaseLink Corporation]
Datasheet
FEATURES
DESCRIPTION
The PLL520-88 (PECL) and PLL520-89 (LVDS) are
VCXO ICs specifically designed to work with
fundamental crystals between 19MHz and 65MHz.
The selectable divide by two feature extends the
operation range from 9.5MHz to 65MHz. They
require very low current into the crystal resulting in
better overall stability. The OE logic feature allows
selection of enable high or enable low.
BLOCK DIAGRAM
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 1
VCON
19MHz to 65MHz fundamental crystal input.
Output range: 9.5MHz – 65MHz
Complementary outputs: PECL or LVDS output.
Selectable OE Logic (enable high or enable low).
Integrated variable capacitors.
Supports 2.5V or 3.3V Power Supply.
Available in 16 pin TSSOP package.
X+
X-
PLL520-8X Block Diagram
Integrated
Oscillator
Amplifier
Varicaps
with
S2
O
Q
Q
Low Phase Noise VCXO (9.5-65MHz)
PIN CONFIGURATION
OUTPUT SELECTION AND ENABLE
Input selection: Bond to GND to set to “0”, bond to VDD to set to “1”
OE_CTRL:
OUTPUT FREQUENCY DIVIDE BY
TWO SELECTOR
OE_SELECT
1 (Default)
0
Preliminary
S2
0
1
VCON
XOUT
GND
VDD
DNC
No connection results to “default” setting through
internal pull-up/-down.
Logical states defined by PECL levels if
OE_SELECT is “1”
Logical states defined by CMOS levels if
OE_SELECT is “0”
XIN
OE
S2
1 (Default)
0 (Default)
OE_CTRL
PLL520-88/-89
0
1
1
2
3
4
5
6
7
8
Tri-state
Output enabled
Output enabled
Tri-state
16
15
14
13
12
11
10
9
Intput/2
Output
Input
State
DNC
DNC
GNDBUF
QBAR
VDDBUF
Q
GNDBUF
GND

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P520-88OC Summary of contents

Page 1

FEATURES • 19MHz to 65MHz fundamental crystal input. • Output range: 9.5MHz – 65MHz • Complementary outputs: PECL or LVDS output. • Selectable OE Logic (enable high or enable low). • Integrated variable capacitors. • Supports 2.5V or 3.3V Power ...

Page 2

PIN AND PAD ASSIGNMENT Name Pin# VDD 1 Power Supply. XIN 2 Crystal input. See Crystal Specification on page 3. XOUT 3 Crystal output. See Crystal Specification on page 3. DNC 4 Do Not Connect. Output Divide by Two selector ...

Page 3

Crystal Specifications PARAMETERS Crystal Resonator Frequency Crystal Loading Rating Interelectrode Capacitance Recommended ESR Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. 3. Voltage Control Crystal Oscillator (3.3V) ...

Page 4

Jitter Specifications PARAMETERS Period jitter RMS at 27MHz Period jitter peak-to-peak at 27MHz Accumulated jitter RMS at 27MHz Accumulated jitter peak-to-peak at 27MHz Random Jitter Measured on Wavecrest SIA 3000 6. Phase Noise Specifications PARAMETERS FREQUENCY Phase Noise relative ...

Page 5

LVDS Electrical Characteristics PARAMETERS Output Differential Voltage V Magnitude Change DD Output High Voltage Output Low Voltage Offset Voltage Offset Magnitude Change Power-off Leakage Output Short Circuit Current 8. LVDS Switching Characteristics PARAMETERS Differential Clock Rise Time Differential Clock ...

Page 6

PECL Electrical Characteristics PARAMETERS SYMBOL Output High Voltage Output Low Voltage 11. PECL Switching Characteristics PARAMETERS Clock Rise Time Clock Fall Time PECL Levels Test Circuit OUT 50Ω 50Ω OUT OUT 80% 50% 20% OUT 47745 Fremont Blvd., Fremont, ...

Page 7

... Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 7 Preliminary Low Phase Noise VCXO (9.5-65MHz 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER PLL520- Marking P520-88 OC P520-88 OC P520-89 OC P520-89 OC PLL520-88/- TEMPERATURE C=COMMERCIAL I=INDUSTRIAL PACKAGE TYPE O=TSSOP Package Option TSSOP – ...

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