M12L128324A-6BG ESMT [Elite Semiconductor Memory Technology Inc.], M12L128324A-6BG Datasheet
M12L128324A-6BG
Related parts for M12L128324A-6BG
M12L128324A-6BG Summary of contents
Page 1
... Non-Pb-free of ordering information Revision 1.0 (Dec. 22 2005) -Delete “Preliminary” from datasheet -Add 90BGA Packing Dimension Revision 1.1 (Feb. 14 2006) -Modify ICC4, ICC5 spec Revision 1.2 (Mar. 14 2006) -Modify ICC2N, ICC3N spec Elite Semiconductor Memory Technology Inc. M12L128324A Publication Date: Mar. 2006 Revision: 1.2 1/47 ...
Page 2
... Elite Semiconductor Memory Technology Inc. M12L128324A Bit x 4 Banks Synchronous DRAM ORDERING INFORMATION Product No. MAX FREQ. PACKAGE COMMENTS M12L128324A-6TG 166MHz 86L TSOPII M12L128324A-7TG 143MHz 86L TSOPII M12L128324A-6BG 166MHz 90 FBGA M12L128324A-7BG 143MHz 90 FBGA Publication Date: Mar. 2006 Revision: 1.2 Pb-free Pb-free Pb-free Pb-free 2/47 ...
Page 3
... CAS L VDDQ DQ8 VSS VDD M VSSQ DQ10 DQ9 DQ6 N VSSQ DQ12 DQ14 DQ1 P DQ11 VDDQ VSSQ VDDQ VSSQ DQ4 R DQ13 DQ15 VSS VDD M12L128324A 8 9 DQ16 VSSQ A0 A1 BA1 A11 CS RAS DQM0 WE DQ7 VSSQ DQ5 VDDQ DQ3 VDDQ DQ0 DQ2 Publication Date: Mar. 2006 Revision: 1 ...
Page 4
... RAS low. Enables row access & precharge. Latches column address on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS , WE active. M12L128324A DQM0~3 DQ Publication Date: Mar. 2006 Revision: 1.2 4/47 ...
Page 5
... ≤ 10ns acceptable. ≤ 10ns acceptable 0.3V, all other pins are not under test = 0V. DD ≤ OUT DD M12L128324A INPUT FUNCTION after the clock and masks the output. SHZ Value Unit -1.0 ~ 4.6 V -1.0 ~ 4.6 V ° -55 ~ +150 ° ) Max Unit Note 3 ...
Page 6
... CKE V (min), CLK V (max), tcc = IH IL input signals are stable IOL = 0 mA Page Burst 2 Banks activated CK(min) ≥ RC(min) ≤ CKE 0.2V M12L128324A Min Max CAS Version Latency -6 -7 120 100 10ns cc 25 ∞ ...
Page 7
... RCD(min RP(min RAS(min) t (max) 100 RAS t 60 RC(min RFC(min CDL(min RDL(min BDL(min) M12L128324A = ° Unit Vtt = 1.4V 50 Ω Z0 =50 30pF (Fig Output Load Circuit Unit Note - ...
Page 8
... Min Max 6 1000 5 SAC - SLZ 5 SHZ - 17 M12L128324A Unit Note -7 CLK Unit Min Max 7 8.6 1000 2 2 Publication Date: Mar ...
Page 9
... RC RAS RP RRD 63ns 42ns 20ns 14ns M12L128324A (Unit : number of clock RCD CCD CDL RDL 18ns 6ns 6ns 12ns ...
Page 10
... X X Exit Entry Exit Valid , X = Don’t Care Logic High , L = Logic Low ) M12L128324A DQM BA0,1 A10/ CODE Row Address ...
Page 11
... Reserved Reserved Reserved Reserved Reserved M12L128324A CAS Latency BT Burst Length Type Sequential Interleave Reserved Reserved Reserved Reserved ...
Page 12
... M12L128324A Interleave Interleave ...
Page 13
... The minimum number of clock cycles required between bank activate and read or write command should be calculated by dividing t clock and then rounding of the result to the next higher integer. M12L128324A RAS and from the time of bank activation. with cycle time of the RCD (min) Publication Date: Mar. 2006 Revision: 1 ...
Page 14
... Four banks can be precharged at the same time by using Precharge all command. Asserting low RAS , and WE with high on A10/AP after all banks have satisfied t banks. At the end of t banks are in idle state. M12L128324A is satisfy from the RAS (min) RP (max). Therefore, RAS and “ ...
Page 15
... NOP’s for a minimum time of t reaches idle state to begin normal operation recommended to use burst 40% auto refresh cycles immediately recommended to use burst 4096 auto refresh cycles immediately before and after exiting self refresh. M12L128324A before the SDRAM RC before and after ...
Page 16
... Mode register set command ( CS , RAS , CAS , WE = Low) The M12L128324A has a mode register that defines how the device operates. In this command, A0 through A10 and BA0~BA1 are the data input pins. After power on, the mode register set command must be executed to initialize the device. ...
Page 17
... Before executing CBR refresh, all banks must be precharged. After this cycle, all banks will be in the idle (precharged) state and ready for a row activate command. During t period (from refresh command to refresh or activate command), the RC M12L128324A cannot accept any other command. Elite Semiconductor Memory Technology Inc. M12L128324A CLK H CKE ...
Page 18
... CS , RAS , CAS , CKE = Low , WE = High) After the command execution, self refresh operation continues while CKE remains low. When CKE goes to high, the M12L128324A exits the self refresh mode. During self refresh mode, refresh interval and refresh operation are performed internally, so there is no need for external control. ...
Page 19
... M12L128324A ...
Page 20
... M12L128324A ...
Page 21
... D Q Elite Semiconductor Memory Technology Inc M12L128324A D 3 Publication Date: Mar. 2006 Revision: 1.2 21/47 ...
Page 22
... M12L128324A Publication Date: Mar. 2006 Revision: 1.2 22/47 ...
Page 23
... M12L128324A ...
Page 24
... M12L128324A ...
Page 25
... from self refresh exit command, any other command can not be accepted. M12L128324A Publication Date: Mar. 2006 Revision: 1.2 ...
Page 26
... During read/write burst with auto precharge, RAS interrupt can not be issued. Before the end of burst, new read/write stops read/write burst and starts new read/write burst. During read/write burst with auto precharge, CAS interrupt can not be issued. M12L128324A Publication Date: Mar. 2006 Revision: 1.2 26/47 ...
Page 27
... NOP (Continue Burst to End ILLEGAL X BA CA, A10/AP ILLEGAL X BA RA, RA10 ILLEGAL ILLEGAL M12L128324A ACTION Row Active) Row Active) Row active Row Active) Row Active) Row active Precharge) Precharge) Precharge) Precharge) Publication Date: Mar. 2006 Revision: 1.2 27/47 Note ...
Page 28
... X X NOP ILLEGAL ILLEGAL ILLEGAL BA = Bank Address CA = Column Address M12L128324A ACTION Idle after t RP Idle after t RP Idle after t RDL Row Active after t RCD Row Active after t RCD Idle after t RC Idle after t RC Idle after 2clocks Idle after 2clocks AP = Auto Precharge Publication Date: Mar ...
Page 29
... Begin Clock Suspend next cycle Exit Clock Suspend next cycle Maintain Clock Suspend must be satisfy before any command other than exit. SS M12L128324A ACTION Note Idle after t (ABI Idle after t (ABI ABI 7 ABI ...
Page 30
... M12L128324A ...
Page 31
... Enable auto precharge , precharge bank B at end of burst. 0 Enable auto precharge , precharge bank C at end of burst. 1 Enable auto precharge , precharge bank D at end of burst. Precharge 0 Bank A 1 Bank B 0 Bank C 1 Bank D X All Banks M12L128324A Publication Date: Mar. 2006 Revision: 1.2 31/47 ...
Page 32
... Elite Semiconductor Memory Technology Inc M12L128324A ...
Page 33
... *Note3 Qa1 Qa0 Qa2 Qa3 Precharge Row Active (A-Ban k) (A- Bank) ) after the clock. SHZ M12L128324A Db2 Db1 Db3 Db0 Db1 Db0 Db2 Db3 *Note3 W rite (A- Bank) Publication Date: Mar. 2006 Revision: 1 ...
Page 34
... Read ( A - Bank ) before row precharge , will be written. RDL M12L128324A ...
Page 35
... M12L128324A ...
Page 36
... M12L128324A ...
Page 37
... Precharge (A-Bank) Row Active (D-Bank) M12L128324A ...
Page 38
... Read with Auto Precharge Bank ) before internal precharge start. RAS M12L128324A ...
Page 39
... Elite Semiconductor Memory Technology Inc M12L128324A ...
Page 40
... M12L128324A ...
Page 41
... M12L128324A ...
Page 42
... prior to Row active command. SS M12L128324A ...
Page 43
... required before exit from self refresh. RAS M12L128324A ...
Page 44
... CS , RAS , CAS , & WE activation at the same clock cycle with address key will set internal mode register. 2. Minimum 2 clock cycles should be met before new RAS activation. 3. Please refer to Mode Register Set table. Elite Semiconductor Memory Technology Inc. Auto Refresh Cycle M12L128324A Publication Date: Mar ...
Page 45
... BSC 0.61 REF 11.76 BSC 10.16 BSC 0.50 0.60 0.80 REF 0.50 BSC 0.25 ° 8 ° ° ° ° M12L128324A Dimension in inch Min Norm Max 0.047 0.002 0.004 0.006 0.037 0.039 0.011 0.007 0.018 0.007 0.008 0.009 0.005 0.008 0.004 0.005 0.006 0.875 BSC 0.024 REF ...
Page 46
... Controlling dimension : Millimeter. Elite Semiconductor Memory Technology Inc. Dimension in mm Dimension in inch Min Norm Max Min 1.40 0.30 0.40 0.012 0.84 0.89 0.94 0.033 0.40 0.50 0.016 7.90 8.00 8.10 0.311 12.90 13.00 13.10 0.508 6.40 11.20 0.80 M12L128324A Norm Max 0.055 0.016 0.035 0.037 0.020 0.315 0.319 0.512 0.516 0.252 0.441 0.031 Publication Date: Mar. 2006 Revision: 1.2 46/47 ...
Page 47
... If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications. Elite Semiconductor Memory Technology Inc. Important Notice M12L128324A Publication Date: Mar. 2006 Revision: 1.2 47/47 ...