EM65568AF EMC [ELAN Microelectronics Corp], EM65568AF Datasheet - Page 95
EM65568AF
Manufacturer Part Number
EM65568AF
Description
130 COM/ 128 SEG 4096 Color STN LCD Driver
Manufacturer
EMC [ELAN Microelectronics Corp]
Datasheet
1.EM65568AF.pdf
(112 pages)
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Relationship of oscillating frequency (fosc) and external clock frequency (fCK) to LCD frame frequency (fFLM) is each
display mode
Original
oscillating clock
When use
built-in
oscillating
circuit (fosc)
When use
external clock
from CK pin.
(fCK)
Pin used:
* This specification is subject to be changed without notice.
※
※
※
※
※
※
※
※
※
※ 10 Oscillating frequency, when using the built-in oscillating circuit (16 gradation fixed display mode)
※ 11 Oscillating frequency, when using the built-in oscillating circuit (8 gradation fixed display mode)
※ 12 Oscillating frequency, when using the built-in oscillating circuit (monochrome display mode)
※ 13 VOUT pin. When using the built-in oscillating circuit, the built-in power supply is used, and boosting 6 times is
※ 14 VOUT pin. When using the built-in oscillating circuit, the built-in power supply is used, and boosting 5 times is
DSEGC0~DSEGC1 , COM0~COM79, COMA, COMB pins Resistance when being applied 0.5V between each
output pin and each power supply (V0, V1, V2, V3, V4) and when being applied 1/9 bias.
(CSB=VDD)
color mode)
used, this pin is applied. VEE=2.4~3.3 V, The electronic control is preset (The code is (“1 1 1 1 1 1 1”)). Measuring
conditions: bias=1/5~1/9, 1/130 duty, without load. RL=500 KΩ (between VOUT and VSS), C1=C2=1.0µF,
C3=0.1µF, DCON=AMPON=”1”, BF=”11”
used, this pin is applied. VEE=2.4~3.3 V, The electronic control is preset (The code is (“1 1 1 1 1 1 1”)). Measuring
conditions: bias=1/5~1/12, 1/130 duty, without load. RL=500 KΩ (between VOUT and VSS), C1=C2=1.0µF,
C3=0.1µF, DCON=AMPON=”1”, BF=”11”
1 D0-D15, CSB, RS, M/S, M86, RDB, WRB, CK, CKS, CLK, LP, FLM, M, P/S, RESB, TEST pins.
2 D0~D15 pins
3 LP, FLM, M, CLK pins
4 CSB, RS, M/S, M86, RDB, WRB, CK, CKS, P/S, RESB, TEST pins
5 VREF pin
6 Applied when D0~D15, CLK, LP, FLM, and M are in the state of high impedance.
7 SEGA0~SEGA127, SEGB0~SEGB127, SEGC0~SEGC127. DSEGA0~DSEGA1, DSEGB0~DSEGB0 ,
8 VDD pin, VDD pin current without load at the stoppage of original oscillating clock and at non-select
9 Oscillating frequency, when using the built-in oscillating circuit (variable gradation display mode,4096 or 256
Display mode
Variable gradation
Simple gradation (4096
color)
Simple gradation (256
color)
Monochrome
Variable gradation
Simple gradation (4096
color)
Simple gradation (256
color)
Monochrome
fosc /(2*31*D) fosc /(4*31*D) fosc /(8*31*D) fosc /(16*31*D)
fosc/(2*15*D)
fosc /(2*7*D)
fosc /(2*1*D)
fCK/(2*31*D)
fCK /(2*15*D) fCK /(4*15*D) fCK /(8*15*D) fCK /(16*15*D)
fCK /(2*7*D)
fCK /(2*1*D)
1/130 to 1/82
130 COM/ 128 SEG 4096 Color STN LCD Driver
95
fosc/(4*15*D)
fosc /(4*7*D)
fosc /(4*1*D)
fCK /(4*31*D) fCK /(8*31*D) fCK /(16*31*D)
fCK /(4*7*D)
fCK /(4*1*D)
Ratio of display duty cycle (1/D)
1/74 to 1/42
fosc/(8*15*D)
fosc /(8*7*D)
fosc /(8*1*D)
fCK /(8*7*D)
fCK /(8*1*D)
1/34 to 1/26
fosc/(16*15*D)
fosc /(16*7*D)
fosc /(16*1*D)
fCK /(16*7*D)
fCK /(16*1*D)
1/18 to 1/10
2005/3/8 (V1.2)
EM65568
Pin used
FLM
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