EM65568AF EMC [ELAN Microelectronics Corp], EM65568AF Datasheet - Page 67
![no-image](/images/no-image-200.jpg)
EM65568AF
Manufacturer Part Number
EM65568AF
Description
130 COM/ 128 SEG 4096 Color STN LCD Driver
Manufacturer
EMC [ELAN Microelectronics Corp]
Datasheet
1.EM65568AF.pdf
(112 pages)
- Current page: 67 of 112
- Download datasheet (2Mb)
8.2 Functions of Control Registers
The EM65568 has many control registers as shown in “7 Control Register”. In case of control register access, upper nibble of
data bus(D7~D4) represent register address, lower nibble of data bus(D3~D0) represent data. The access example is shown in
the following. The Pins (CSB, RS, RDB, WRB) setting are for 80-family MPU interface. Only the setting of terminal
(RDB,WRB) is different, when it is accessed by the 68-fanily MPU.
(Example) X Address
In the writing to the control register, it is used directly as addressing D7~D4 of the data bus. In case of register read, first set
RA register for specific register address, next can read specific register. Therefore, it is need 2-step for register read. Then,
specific register output to D3~D0 of data bus. Except D3~D0 of data bus are all “H”. Prohibit access to undefined register
address area. When RS is “L”, all read/write operations are accessed to display RAM. Then data bus doesn’t include register
address. In case of write, D3~D0 data is written to the register designated at D7~D4 in rising edge of the WRB signal. In case
of read, register can output to data bus is RDB active period. Control register and display RAM are the equal access timing.
8.2.1 X Address Register (AX)
(At the time of reset: {AX3, AX2, AX1, AX0}= 0H, read address: 0H)
(At the time of reset: {AX7, AX6, AX5, AX4}= 0H, read address: 1H)
The AX register set to X-direction address of display RAM. In data setting, lower place and upper place are divided with 4-bit
and 4-bit respectively.
8.2.2 Y Address Register
(At the time of reset: {AY3, AY2, AY1, AY0}=0H, read address: 2H)
* This specification is subject to be changed without notice.
D7
D7
D7
D7
0
0
0
0
D6
D6
0
0
D6
D6
0
0
D7
0
D5
D5
Register address
1
1
D5
D5
0
0
D6
0
D4
D4
0
1
D4
D4
0
1
D5
0
AY3 AX2 AY1 AY0
AY7 AY6 AY5 AY4
D3
D3
AX3
AX7
D3
D3
D4
0
D2
D2
AX3 AX2 AX1 AX0
AX2
AX6
D3
D2
D2
D1
D1
D2
AX1
AX5
D1
D1
D0
D0
Data
D1
AX0
AX4
D0
D0
CSB
CSB
D0
130 COM/ 128 SEG 4096 Color STN LCD Driver
0
0
CSB
CSB
67
0
0
RS
RS
1
1
CSB
0
RS
RS
1
1
RDB WRB RE2 RE1 RE0
RDB WRB RE2 RE1 RE0
1
1
Pins setting
RS
1
RDB WRB RE2
RDB WRB RE2
1
1
0
0
RDB
1
0
0
0
0
WRB
0
0
0
0
0
RE2
RE1
RE1
0
Register Bank
0
0
0
0
RE1
RE0
RE0
0
2005/3/8 (V1.2)
0
0
RE0
0
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