EM65568AF EMC [ELAN Microelectronics Corp], EM65568AF Datasheet - Page 28
![no-image](/images/no-image-200.jpg)
EM65568AF
Manufacturer Part Number
EM65568AF
Description
130 COM/ 128 SEG 4096 Color STN LCD Driver
Manufacturer
EMC [ELAN Microelectronics Corp]
Datasheet
1.EM65568AF.pdf
(112 pages)
- Current page: 28 of 112
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7.9 Segment Display Output Order/Reverse Set up
The order of display output, SEGA0, SEGB0, SEGC0 to SEGA127, SEGB127, and SEGC127 can be reversed. If REF control
bit set to “1”, display by reversing access to display RAM from MPU by using REF register, lessen the limitation in placing IC
when assembling an LCD panel module.
7.10 Relationship between Display RAM and Address
The Display RAM block diagram shows in the figure below:
The EM65568 execute address conversion that depends on control register setting. In case of auto increment mode, usually AX
register is added one. For instance when REF and AXI are both “1”, AX register is added one, but effective X address seems
decrement because of address conversion. The effective Y address use AY register values as it is.
* This specification is subject to be changed without notice.
Bit-order reverse
Write:depend on
Read:depend on
MPU I/F
REF,SWAP
REF
Write
Data
Internal Data Bus
Bit order reverse
X-Address (00H~FFH)
Address conversion circuit
Figure 10. The Display RAM block diagram
Display RAM
Read
AX Register
Data
130 COM/ 128 SEG 4096 Color STN LCD Driver
Grayscale Conversion
Effective X address
Data Conversion
28
Segment data
Data conversion is
depend on MON,
REF,SWAP,GLSB
SEGMENT Output I/F
Valid maximum is depend on
MON,WLS,WIN,HSW,C256
setting
Address conversion is depend
on MON,WLS,REF setting
2005/3/8 (V1.2)
EM65568
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