PM8610-BIAP PMC [PMC-Sierra, Inc], PM8610-BIAP Datasheet - Page 314

• Manufacturer Part Number: PM8610-BIAP
• Description: SBS Telecom Standard Product Data Sheet Preliminary
• Manufacturer: PMC [PMC-Sierra, Inc]

14.6
14.7
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000168, Issue 3
TC1FP(TJ0J1V1)
TDATA[7:0]
Transmit TelecomBus Functional Timing
The delay from the Incoming TelecomBus, either four by 19.44 MHz buses or one 77.76 MHz
bus, to the transmit TelecomBus is the same as the delay to the serial LVDS interface. There is a
slight difference in the overall delay since the fifos of the serial LVDS link are no longer in the
path and therefore the absolute delay is more controlled. The total delay is from the incoming
TelecomBus to the transmit TelecomBus is 1080+12 77.76 MHz SYSCLK cycles.
Figure 38 shows the transmit TelecomBus functional timing. The transmit TelecomBus has only a
couple of small differences from the incoming 77.76 MHz TelecomBus, in fact without column
switching they could be identical. The main functional difference is in how the TC1FP(TJ0J1V1)
signal is handled. TJ0J1V1 will pulse during the J0 byte position, but must be configured to
pulse during the J1 and V1 positions if desired. This is shown in Figure 38.
Figure 38 Transmit TelecomBus Functional Timing
Transmit SBI336 Bus Functional Timing
The delay from the Incoming SBI/SBI336 bus to the transmit SBI336 bus is the same as the delay
to the serial LVDS interface. There is a slight difference in the overall delay since the FIFOs of
the serial LVDS link are no longer in the path and therefore the absolute delay is more controlled.
When switching SBI tributaries the total delay is 1080+12 SYSCLK cycles. When switching
DS0s the data delay is 9720+12 SYSCLK cycles and the CAS delay is the T1 or E1 multiframe +
12 clocks.
The transmit SBI336 interface is functionally the same as the incoming 77.76 MHz SBI336
interface. Figure 39 shows the transmit SBI336 bus timing. Like Figure 32 it shows positive and
negative timing adjustments via the TPL signal, a V5 tributary frame alignment and positive and
negative justification requests via TJUST_REQ.
SYSCLK
TTAIS
TTPL
TDP
TPL
TV5
S4,3
A2
S1,1
J0
S2,1
Z0
S3,1
Z0
S4,1
Z0
S1,2
Z0
S2,2
Z0
S3,2
Z0
S4,2
Z0
S1,3
Z0
S2,3
Z0
S3,3
Z0
S4,3
Z0
B522
S1,1
B522
S2,1
B522
S3,1
B522
S4,1
S4,3
H2
SBS Telecom Standard Product Data Sheet
S1,1
H3
S2,1
H3
S3,1
H3
S4,1
H3
S1,2
H3
S2,2
H3
S3,2
H3
S4,2
H3
S1,3
H3
S2,3
H3
S3,3
H3
S4,3
H3
S1,1
B0
S2,1
B0
Preliminary
S3,1
B0
S4,1
B0
S1,2
B0
S2,2
B0
314
S3,2
B0