PM8610-BIAP PMC [PMC-Sierra, Inc], PM8610-BIAP Datasheet - Page 18

• Manufacturer Part Number: PM8610-BIAP
• Description: SBS Telecom Standard Product Data Sheet Preliminary
• Manufacturer: PMC [PMC-Sierra, Inc]

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000168, Issue 3
Permits any receive or incoming byte from an input port to be mapped to any outgoing or
transmit byte, respectively, on the associated output port through the Memory switch.
Supports redundant working and protect serial SBI336S links in support of a redundant
Memory:Space:Memory switch with the NSE.
Encodes and decodes byte wide SBI and SBI336 bus control signals for all SBI supported
link types and clock modes for transport over the serial SBI336S interface.
Encodes data from the incoming SBI bus or TelecomBus stream to a working and protect
777.6 Mbit/s LVDS serial links with 8B/10B-based encoding.
Decodes data from a working and protect 777.6 MHz LVDS serial links with 8B/10B-based
encoding to the outgoing SBI bus or TelecomBus stream.
In SBI mode, switches Channel Associated Signaling bits (CAS) with all DS0 data.
Uses 8B/10B-based line coding protocol on the serial links to provide transition density
guarantee and DC balance and to offer a greater control character vocabulary than the
standard 8B/10B protocol.
Provides optional pseudo-random bit sequence (PRBS) generation for each outgoing LVDS
serial data link for off-line link verification. PRBS can be inserted with STS-1 granularity.
Provides PRBS detection for each incoming LVDS serial link for off-line link verification.
PRBS is verified with STS-1 granularity.
Provides pins to coordinate updating of the connection map of the time-slot interchange
blocks in the local device, peer SBS devices and companion NSE switch device.
Can communicate with the NSE switch device over an in-band communications channel in
the LVDS links. This channel includes mechanisms for central control and configuration.
Derives all internal timing from a single 77.76 MHz system clock and a system frame pulse.
Implemented in 1.8 V/3.3 V 0.18 m CMOS and packaged in a 352 ball 27 mm x 27 mm
UBGA package.
Consumes low power at 1.4 W.
SBS Telecom Standard Product Data Sheet
Preliminary
18