PXA250 INTEL [Intel Corporation], PXA250 Datasheet - Page 24

• Manufacturer Part Number: PXA250
• Description: Intel-R PXA250 and PXA210 Applications Processors
• Manufacturer: INTEL [Intel Corporation]

PXA250 and PXA210 — Electrical, Mechanical, and Thermal Specification
24
Table 4.
Pin and Signal Descriptions for the PXA210 Applications Processor (Sheet 6 of 7)
Miscellaneous Pins
BOOT_SEL
[2:0]
PWR_EN
nBATT_FAULT
nVDD_FAULT
nRESET
nRESET_OUT
JTAG and Test Pins
nTRST
TDI
TDO
TMS
TCK
TEST
TESTCLK
Power and Ground Pins
VCC
VSS
PLL_VCC
PLL_VSS
VCCQ
Pin Name
IC
OC
IC
IC
IC
OC
IC
IC
OCZ
IC
IC
IC
IC
SUP
SUP
SUP
SUP
SUP
Type
Boot select pins. (input) Indicates type of boot device.
Power Enable for the power supply. (output) When negated, it signals the power
supply to remove power because the system is entering Sleep Mode.
Main Battery Fault. (input) Signals that main battery is low or removed. Assertion
causes the PXA210 applications processor to enter Sleep Mode or force an
Imprecise Data Exception, which cannot be masked. The PXA210 applications
processor will not recognize a wakeup event while this signal is asserted.
VDD Fault. (input) Signals that the main power source is going out of regulation.
nVDD_FAULT causes the PXA210 applications processor to enter Sleep Mode or
force an Imprecise Data Exception, which cannot be masked. nVDD_FAULT is
ignored after a wakeup event until the power supply timer completes
(approximately 10 ms).
Hard reset. (input) Level sensitive input used to start the processor from a known
address. Assertion causes the current instruction to terminate abnormally and
causes a reset. When nRESET is driven high, the processor starts execution from
address 0. nRESET must remain low until the power supply is stable and the
internal 3.6864 MHz oscillator has stabilized.
Reset Out. (output) Asserted when nRESET is asserted and deasserts after
nRESET is deasserted but before the first instruction fetch. nRESET_OUT is also
asserted for “soft” reset events: sleep, watchdog reset, or GPIO reset.
JTAG Test Interface Reset. Resets the JTAG/Debug port. If JTAG/Debug is used,
drive nTRST from low to high either before or at the same time as nRESET. If
JTAG is not used, nTRST must be either tied to nRESET or tied low. Intel
recommends that a JTAG/Debug port be added to all systems for debug and
download. See Chapter 9 in the “Intel® PXA250 and PXA210 Applications
Processor Design Guide” for details.
JTAG test data input. (input) Data from the JTAG controller is sent to the PXA210
using this pin. This pin has an internal pull-up resistor.
JTAG test data output. (output) Data from the PXA210 applications processor is
returned to the JTAG controller using this pin.
JTAG test mode select. (input) Selects the test mode required from the JTAG
controller. This pin has an internal pull-up resistor.
JTAG test clock. (input) Clock for all transfers on the JTAG test interface.
Test Mode. (input) Reserved. Must be grounded.
Test Clock. (input) Reserved. Must be grounded.
Positive supply for internal logic. Must be connected to the low voltage (.85 -
1.3v) supply on the PCB.
Ground supply for internal logic. Must be connected to the common ground
plane on the PCB.
Positive supply for PLLs and oscillators. Must be connected to a separate quiet
supply plane on the PCB but may be connected to the common low voltage supply.
Ground signal for PLLs.
Positive supply for all CMOS I/O except memory bus. Must be connected to the
common 3.3 V supply on the PCB.
Signal Descriptions
Datasheet