PXA250 INTEL [Intel Corporation], PXA250 Datasheet - Page 14

• Manufacturer Part Number: PXA250
• Description: Intel-R PXA250 and PXA210 Applications Processors
• Manufacturer: INTEL [Intel Corporation]

PXA250 and PXA210 — Electrical, Mechanical, and Thermal Specification
14
Table 2.
Pin and Signal Descriptions for the PXA250 Applications Processor (Sheet 6 of 7)
Miscellaneous Pins
BOOT_SEL
[2:0]
PWR_EN
nBATT_FAUL T
nVDD_FAULT
nRESET
nRESET_OUT
JTAG Pins
nTRST
TDI
TDO
TMS
TCK
TEST
Name
Type
OCZ
OCZ
OC
IC
IC
IC
IC
IC
IC
IC
IC
IC
Boot programming select pins. These pins are sampled to indicate the type of
boot device present per the following table;
BOOT_SEL[2:0]
Power Enable. Active high output.
PWR_EN enables the external power supply. Negating it signals the power supply
that the system is going into sleep mode and that the VDD power supply should
be removed.
Battery Fault. Active low input.
Signals the applications processor that the main power source is going away
(battery is low or is removed from the system.) The assertion of nBATT_FAULT
causes the applications processor to enter Sleep Mode. The device will not
recognize a wakeup event while this signal is asserted.
VDD Fault. Active low input.
Signals the applications processor that the main power source is going out of
regulation (i.e. shorted card is inserted). nVDD_FAULT causes the device to enter
Sleep Mode. nVDD_FAULT is ignored after a wakeup event until the power supply
timer completes (approximately 10 ms).
Hard reset. Active low input.
nRESET is a level sensitive input which starts the processor from a known
address. A LOW level causes the current instruction to terminate abnormally, and
all on-chip states to be reset. When nRESET is driven HIGH, the processor re-
starts from address 0. nRESET must remain LOW until the power supply is stable
and the internal 3.6864 MHz oscillator has come up to speed. While nRESET is
LOW the processor performs idle cycles.
Reset Out. Active low output.
This signal is asserted when nRESET is asserted and deasserts after nRESET is
negated but before the first instruction fetch. nRESET_OUT is also asserted for
“soft” reset events (sleep, watchdog reset, GPIO reset)
JTAG Test interface reset. If JTAG is used, then you must drive nTRST from low
to high either before or at the same time as nRESET
If JTAG is not used, then tie nTRST to either nRESET or low.
JTAG test interface data input. Note this pin has an internal pullup resistor.
JTAG test interface data output. Note this pin does NOT have an internal pullup
resistor.
JTAG test interface mode select. Note this pin has an internal pullup resistor.
JTAG test interface reference Clock. TCK is the reference clock for all transfers
on the JTAG test interface. Note this pin has an internal pulldown resistor.
Test Mode. You must ground this pin. This pin is for manufacturing purposes only.
000
001
010
011
100
101
110
111
Description
Asynchronous 32-bit ROM
Asynchronous 16-bit ROM
Reserved
Reserved
One 32-bit SMROM
One 16 bit SMROM
Two 16 bit SMROMs (32 bit bus)
Reserved
Description
Datasheet