M12L16161A-4.3T ETC, M12L16161A-4.3T Datasheet - Page 9

• Manufacturer Part Number: M12L16161A-4.3T
• Description: 512K x 16Bit x 2Banks Synchronous DRAM
• Manufacturer: ETC

Burst Length and Sequence
(Burst of Two)
(Burst of Four)
(Burst of Eight)
POWER UP SEQUENCE
1.Apply power and start clock, attempt to maintain CKE= “H”, L(U)DQM = “H” and the other pin are NOP condition at the
2.Maintain stable power, stable clock and NOP input condition for a minimum of 200us.
3.Issue precharge commands for all banks of the devices.
4.Issue 2 or more auto-refresh commands.
5.Issue mode register set command to initialize the mode register.
Cf.)Sequence of 4 & 5 is regardless of the order.
Elite Semiconductor Memory Technology Inc.
inputs.
Full page burst is an extension of the above tables of Sequential Addressing, with the length being 256 for 1Mx16 divice.
(column address A2-A0, binary)
(column address A1-A0, binary)
(column address A0 binary)
Starting Address
Starting Address
Starting Address
000
001
010
100
101
011
110
111
00
01
10
11
0
1
Sequential Addressing
Sequential Addressing
Sequential Addressing
Sequence (decimal)
Sequence (decimal)
Sequence (decimal)
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 4, 5, 6, 7, 0
2, 3, 4, 5, 6, 7, 0, 1
3, 4, 5, 6, 7, 0, 1, 2
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 0, 1, 2, 3, 4
6, 7, 0, 1, 2, 3, 4, 5
7, 0, 1, 2, 3, 4, 5, 6
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
0, 1
1, 0
P.9
Publication Date : Jan. 2000
Interleave Addressing
Interleave Addressing
Interleave Addressing
Sequence (decimal)
Sequence (decimal)
Sequence (decimal)
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
M12L16161A
0, 1
1, 0
Revision : 1.3u