M12L16161A-4.3T ETC, M12L16161A-4.3T Datasheet - Page 25

• Manufacturer Part Number: M12L16161A-4.3T
• Description: 512K x 16Bit x 2Banks Synchronous DRAM
• Manufacturer: ETC

Self Refresh Entry & Exit Cycle
*Note: TO ENTER SELF REFRESH MODE
Elite Semiconductor Memory Technology Inc.
C L O C K
A 1 0 / A P
A D D R
C A S
D Q M
R A S
C K E
W E
B A
DQ
C S
TO EXIT SELF REFRESH MODE
1. CS , RAS & CAS with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don’t care except for CKE.
3. The device remains in self refresh mode as long as CKE stays “Low”.
4. System clock restart and be stable before returning CKE high.
5. CS Starts from high.
6. Minimum t
7.2K cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst
cf.) Once the device enters self refresh mode, minimum
refresh.
0
S e l f R e f r e s h E n t r y
1
* N o t e 1
t
S S
RC
2
H i - Z
is required after CKE going high to complete self refresh exit.
* N o t e 2
3
4
5
6
*Note3
7
8
9
t
* N o t e 4
10
P.25
RAS
H i - Z
S e l f R e f r e s h E x i t
is required before exit from self refresh.
11
* N o t e 5
12
13
t
R C m i n
14
Publication Date : Jan. 2000
* N o t e 6
A u t o R e f r e s h
15
* N o t e 7
16
M12L16161A
17
Revision : 1.3u
: D o n ' t c a r e
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