DM8603EP DAVICOM [Davicom Semiconductor, Inc.], DM8603EP Datasheet - Page 30

• Manufacturer Part Number: DM8603EP
• Description: 10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
• Manufacturer: DAVICOM [Davicom Semiconductor, Inc.]

7.2.3
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
PHY_ADR
08h, 09h, 0Ah
10:9
Bit
14
15
13
12
11
8
7
6
5
4
Per Port Basic Control Register 2 (112h, 132h, 152h)
A1h.[15]
A1h.[14]
A1h.[13]
A1h.[12]
A1h.[11]
81h.[15]
91h.[15]
81h.[14]
91h.[14]
81h.[13]
91h.[13]
81h.[12]
91h.[12]
81h.[11]
91h.[11]
A1h.[8]
A1h.[7]
A1h.[6]
A1h.[5]
A1h.[4]
81h.[8]
91h.[8]
81h.[7]
91h.[7]
81h.[6]
91h.[6]
81h.[5]
91h.[5]
81h.[4]
91h.[4]
ROM
---
REG_ADR
12h
PSE,RW
PSE,RW
PSE,RW
PSE,RW
PSE,RW
PSE,RW
PSE,RW
PSE,RW
PSE,RW
PSE,RW
Type
RO
Default
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
00b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
ABS_ADR
112h, 132h, 152h
NO_DIS_RX
Not Discard RX Packets when Ingress Bandwidth Control
When received packets bandwidth reach Ingress bandwidth
threshold, the packets over the threshold are not discarded but with
flow control.
BANDWIDTH
Bandwidth Control Mode
STORM_UUP
Broadcast Storm Enable for Unlearned Unicast Packets
STORM_MP
Broadcast Storm Filtering for Multicast Packets
Treat multicast packet as source of storm
MIRR_DBP
Don't Mirror Broadcast/Multicast Packets
If Mirror Function is Enabled
RESERVED
Write as 00b, ignore when read
FIR_UUDMAC
Filter Packets with Unlearned Unicast DMAC
FIR_UMDMAC
Filter Packets with Unlearned Multicast DMAC
FIR_BDMAC
Filter Packets with Broadcast DMAC
FIR_MDMAC
Filter Packets with Multicast DMAC
FIR_MSMAC
Filter Packets with Multicast SMAC
0: Disable
1: Enable
0: Separate mode. Bandwidth control with ingress and egress is
1: Combined mode. Bandwidth control with ingress or egress is
0: Disable
1: Enable
0: Disable
1: Enable
0: Broadcast/Multicast would be mirrored
1: Broadcast/Multicast would not be mirrored
0: Disable
1: Enable
0: Disable
1: Enable
0: Disable
1: Enable
0: Disable
1: Enable
separated, the threshold defined in REG 08/09/0Ah.15h.[15:8]
combined, the threshold defined in REG 08/09/0Ah.15h.[3:0]
Description
DM8603
30