CH7007A-V ETC, CH7007A-V Datasheet - Page 5

• Manufacturer Part Number: CH7007A-V
• Description: DIGITAL PC TO TV ENCODER WITH MACROVISION
• Manufacturer: ETC

CHRONTEL
201-0000-002 Rev. 2.7, 08/23/2000
Table 1. Pin Descriptions
14,24,34,
11,22,36
44-Pin
PLCC
25,29
32
33
35
38
39
41
43
42
31
37
40
44
8,18,28,
44-Pin
5,16,30
TQFP
19,23
26
27
29
32
33
35
37
36
25
31
34
38
Power
Power
Power
Power
Power
Power
Power
In/Out
In/Out
Type
Out
Out
In
In
In
Symbol
DS/BCO
RESET*
DVDD2
P-OUT
XI/FIN
DVDD
DGND
AGND
AVDD
GND
VDD
XO
SD
SC
Pixel Clock Output
This pin provides a pixel clock signal to the VGA controller (adjustable as
1X, 2X and 3X) and is driven from the DVDD2 supply. This clock will only
be provided in master clock modes, and will be tri-stated otherwise, (see
the section on Digital Video Interface and Registers and Programming
for more details). The capacitive loading on this pin should be kept to a
minimum.
Serial Data Input/Output
This pin functions as the serial data pin of the I
uses the DVDD supply.
(see the I
Serial Clock Input
This pin functions as the serial clock pin of the I
uses the DVDD supply.
(see the I
Reset* Input
When this pin is low, the CH7007 is held in the power-on reset
condition. When this pin is high, the device operates normally and reset
is controlled through the I
Crystal Input/External Reference Input
A parallel resonance 14.31818MHz crystal should be attached
between this pin and XO. However, an external CMOS clock can be
attached to XI/FIN.
Crystal Output
A parallel resonance 14.31818MHz +20ppm crystal should be
attached between this pin and XI/FIN. However, if an external CMOS
clock is attached to XI/FIN, XO should not be connected.
Data start (input)/Buffered Clock (output)
In normal operating modes, when configured as an input, the rising
edge of this signal identifies the first active pixel of data for each
active line. The level is 0 to DVDD2, with VREF as the threshold level.
When configured as an output this pin provides a buffered clock
output, driven by the DVDD supply. The output clock can be selected
using the BCO register (17th) (see Registers and Programing).
Digital Supply Voltage
Digital Ground
DAC
DAC Supply Voltage
PLL Supply Voltage
PLL Ground
I/O SUPPLY VOLTAGE
Digital supply voltage for the P-OUT
2
2
C Port Operation section for details)
C Port Operation section for details)
2
C register.
Description
2
2
C interface port, and
C interface port, and
CH7007A
5