CH7007A-V ETC, CH7007A-V Datasheet - Page 40

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CH7007A-V

Manufacturer Part Number
CH7007A-V
Description
DIGITAL PC TO TV ENCODER WITH MACROVISION
Manufacturer
ETC
Datasheet
CHRONTEL
Subcarrier Value Registers
The lower four bits of registers 18H through 1FH contain a 32-bit value which is used as an increment value for the
ROM address generation circuitry. The bit locations are specified as the following:
Register
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
40
Register Descriptions (continued)
Table 22. Clock Output Selection
Table 23. K3 Selection
SCO[2:0]
000
001
010
011
100
101
110
111
Bit:
Symbol:
Type:
Default:
SHF[2:0]
000
010
011
100
101
110
111
7
Contents
FSCI[31:28]
FSCI[27:24]
FSCI[23:20]
FSCI[19:16]
FSCI[15:12]
FSCI[11:8]
FSCI[7:4]
FSCI[3:0]
Buffered Clock Output
(for test use only)
VCO divided by K3 (see Table23 )
Field ID signal
(for test use only)
(for test use only)
TV horizontal sync (for test use only)
TV vertical sync (for test use only)
14MHz crystal
K3
2.5
3.5
4.5
4
5
6
7
6
5
4
3
FSCI#
R/W
2
FSCI#
201-0000-002 Rev. 2.7, 08/23/2000
R/W
Symbol: FSCI
Address: 18H - 1FH
Bits: 4 or 8 each
1
FSCI#
R/W
CH7007A
0
FSCI#
R/W

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