CH7007A-V ETC, CH7007A-V Datasheet - Page 39

• Manufacturer Part Number: CH7007A-V
• Description: DIGITAL PC TO TV ENCODER WITH MACROVISION
• Manufacturer: ETC

Register Descriptions (continued)
PLL N Value Register
The PLL N value register determines the division factor applied to the VCO output before being applied to the PLL
phase detector, when the CH7007 is operating in master mode. In slave mode, the value of ‘N’ is always 1. This
register contains the lower 8 bits of the complete 10-bit N value. The pixel clock generated in a master mode and is
calculated according to the equation below:
When using a 14.318 MHz frequency reference, the required M and N values for each mode are shown in the table
below
Buffered Clock Output Register
When this pin is selected to be an output, the buffered clock output register determines which clock is selected to be
output at the DS/BCO clock output pin and what frequency value is output when a VCO derived signal is output.
The tables below show the possible outputs.
CHRONTEL
Table 21. M and N Values for Each Mode
201-0000-002 Rev. 2.7, 08/23/2000
Mode
Bit:
Symbol:
Type:
Default:
Bit:
Symbol:
Type:
Default:
10
12
13
11
0
1
2
3
4
5
6
7
8
9
512x384, PAL, 5:4
512x384, PAL, 1:1
512X384, NTSC, 5:4
512X384, NTSC, 1:1
720X400, PAL, 5:4
720X400, PAL, 1:1
720X400, NTSC, 5:4
720X400, NTSC, 1:1
640X400, PAL, 5:4
640X400, PAL, 1:1
640X400, NTSC, 5:4
640x400, NTSC, 1:1
640X400, NTSC, 7:8
640X480, PAL, 5:4
Standard, Scaling Ratio
VGA Resolution, TV
7
N7
R/W
1
7
6
N6
R/W
0
6
N 10-
bits
5
N5
R/W
0
126
110
339
106
108
190
5
SHF2
R/W
0
20
53
70
94
22
20
9
9
Fpixel = Fref* [(N+2) / (M+2)]
M 9-
bits
138
13
89
63
26
63
33
61
63
11
89
13
4
3
4
N4
R/W
0
4
SHF1
R/W
0
Mode
14
15
16
17
18
19
20
21
22
23
24
25
26
3
N3
R/W
0
3
SHF0
R/W
0
640x480, PAL, 1:1
640X480, PAL, 5:6
640X480, NTSC, 1:1
640X480, NTSC, 7:8
640X480, NTSC, 5:6
800X600, PAL, 1:1
800X600, PAL, 5:6
800X600, PAL, 3:4
800X600, NTSC, 5:6
800X600, NTSC, 3:4
800X600, NTSC, 7:10
720X576, PAL, 1:1
720X480, NTSC, 1:1
Standard, Scaling Ratio
VGA Resolution, TV
2
N2
0
2
SCO2
0
R/W
R/W
Symbol: PLLN
Address: 15H
Bits: 8
Symbol: BCO
Address: 17H
Bits: 6
1
N1
R/W
0
1
SCO1
R/W
0
N 10-
bits
CH7007A
110
126
190
647
284
302
86
94
62
31
31
9
9
0
N0
R/W
0
0
SCO0
R/W
0
M 9-
bits
313
103
63
63
89
33
33
19
89
33
33
4
3
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