HY5DU561622ALT-K HYNIX [Hynix Semiconductor], HY5DU561622ALT-K Datasheet - Page 29

• Manufacturer Part Number: HY5DU561622ALT-K
• Description: 256M-S DDR SDRAM
• Manufacturer: HYNIX [Hynix Semiconductor]

Rev. 0.4/ May. 02
AC CHARACTERISTICS I
Row Cycle Time
Auto Refresh Row Cycle Time
Row Active Time
Active to Read with Auto Precharge Delay
Row Address to Column Address Delay
Row Active to Row Active Delay
Column Address to Column Address Delay
Row Precharge Time
Write Recovery Time
Write to Read Command Delay
Auto Precharge Write Recovery + Precharge Time
System Clock Cycle Time
Clock High Level Width
Clock Low Level Width
Data-Out edge to Clock edge Skew
DQS-Out edge to Clock edge Skew
DQS-Out edge to Data-Out edge Skew
Data-Out hold time from DQS
Clock Half Period
Data Hold Skew Factor
Valid Data Output Window
Data-out high-impedance window from CK,/CK
Data-out low-impedance window from CK, /CK
Input Setup Time (fast slew rate)
Input Hold Time (fast slew rate)
Parameter
(AC operating conditions unless otherwise noted)
CL = 2.5
CL = 2
Symbol
tDQSCK
tDQSQ
tWTR
tRCD
tRRD
tCCD
tQHS
tRFC
tRAS
tRAP
tDAL
tWR
tQH
tRC
tCH
tAC
tHP
tDV
tHZ
tRP
tCK
tCL
tLZ
tIH
tIS
(tCL,tCH)
(tWR/tCK)
(tRP/tCK)
tRCD or
tRPmin
-t
0.45
0.45
0.75
0.75
Min
-0.7
-0.6
-0.7
-0.7
min
7.5
t
60
72
42
18
12
18
15
QHS
HP
1
1
+
6
-
-
t
DDR333
QH
-t
DQSQ
Max
0.55
0.55
0.55
0.45
70K
0.7
0.6
0.7
0.7
12
12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
(tCL,tCH)
(tWR/tCK)
(tRP/tCK)
tRCD or
tRPmin
-t
-0.75
-0.75
-0.75
-0.75
0.45
0.45
Min
min
t
7.5
7.5
0.9
0.9
60
75
45
15
15
15
15
QHS
HP
+
1
1
-
-
t
DDR266
QH
-t
HY5DU56422A(L)T
HY5DU56822A(L)T
HY5DU561622A(L)T
DQSQ
120K
Max
0.55
0.55
0.75
0.75
0.75
0.75
0.75
0.5
12
12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Unit
CK
CK
CK
CK
CK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2,3,5,6
Note
1,10
1,9
29
16
15
10
17