HY5DU561622ALT-K HYNIX [Hynix Semiconductor], HY5DU561622ALT-K Datasheet - Page 18

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HY5DU561622ALT-K

Manufacturer Part Number
HY5DU561622ALT-K
Description
256M-S DDR SDRAM
Manufacturer
HYNIX [Hynix Semiconductor]
Datasheet
Rev. 0.4/ May. 02
7.
8.
Power-Up Sequence
Issue 2 or more Auto Refresh commands.
Issue a Mode Register Set command to initialize the mode register with bit A8 = Low.
VDD
VDDQ
VTT
VREF
/CLK
CLK
CKE
CMD
DM
ADDR
A10
BA0,BA1
DQS
DQ’s
tVTD
VDD and CK stable
T=200usec
Power up
tIS tIH
NOP
Precharge All
*200 cycles of CK are required (for DLL locking) before any executable command can be applied.
PRE
tRP
EMRS Set
EMRS
CODE
CODE
CODE
tMRD
(with A8=H)
Reset DLL
MRS Set
CODE
CODE
CODE
MRS
200 cycles of CK*
NOP
Precharge All
PRE
tRP
Auto Refresh
2 or more
HY5DU56422A(L)T
HY5DU56822A(L)T
HY5DU561622A(L)T
AREF
tRFC
(with A8=L)
MRS Set
CODE
CODE
CODE
MRS
18

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