EM78451AP EMC [ELAN Microelectronics Corp], EM78451AP Datasheet - Page 48

• Manufacturer Part Number: EM78451AP
• Description: 8-Bit Microcontroller
• Manufacturer: EMC [ELAN Microelectronics Corp]

EM78451
8-Bit Microcontroller
44 •
INSTRUCTION BINARY
0 0000 0000 0000
0 0000 0000 0001
0 0000 0000 0010
0 0000 0000 0011
0 0000 0000 0100
0 0000 0000 rrrr
0 0000 0001 0000
0 0000 0001 0001
0 0000 0001 0010
0 0000 0001 0011
0 0000 0001 0100
0 0000 0001 rrrr
0 0000 0010 0000
0 0000 01rr rrrr
0 0000 1000 0000
0 0000 11rr rrrr
0 0001 00rr rrrr
0 0001 01rr rrrr
0 0001 10rr rrrr
0 0001 11rr rrrr
0 0010 00rr rrrr
0 0010 01rr rrrr
0 0010 10rr rrrr
0 0010 11rr rrrr
0 0011 00rr rrrr
0 0011 01rr rrrr
0 0011 10rr rrrr
0 0011 11rr rrrr
0 0100 00rr rrrr
0 0100 01rr rrrr
0 0100 10rr rrrr
0 0100 11rr rrrr
0 0101 00rr rrrr
0 0101 01rr rrrr
0 0101 10rr rrrr
0 0101 11rr rrrr
0 0110 00rr rrrr
0 0110 01rr rrrr
(2). The I/O register can be regarded as general register. That is, the same instruction
can operate on I/O register.
The symbol "R" represents a register designator that specifies which one of the
registers (including operational registers and general purpose registers) is to be utilized
by the instruction. Bits 6 and 7 in R4 determine the selected register bank. "b"
represents a bit field designator that selects the value for the bit, located in the register
"R" and affects by the operation. "k" represents an 8 or 10-bit constant or literal value.
0000
0001
0002
0003
0004
0010
0011
0012
0013
0014
0020
0080
HEX
000r
001r
00rr
00rr
01rr
01rr
01rr
01rr
02rr
02rr
02rr
02rr
03rr
03rr
03rr
03rr
04rr
04rr
04rr
04rr
05rr
05rr
05rr
05rr
06rr
06rr
NOP
DAA
CONTW
SLEP
WDTC
IOW R
ENI
DISI
RET
RETI
CONTR
IOR R
TBL
MOV R,A
CLRA
CLR R
SUB A,R
SUB R,A
DECA R
DEC R
OR A,R
OR R,A
AND A,R
AND R,A
XOR A,R
XOR R,A
ADD A,R
ADD R,A
MOV A,R
MOV R,R
COMA R
COM R
INCA R
INC R
DJZA R
DJZ R
RRCA R
RRC R
MNEMONIC
No Operation
A → CONT
0 → WDT, Stop oscillator
0 → WDT
A → IOCR
Disable Interrupt
[Top of Stack] → PC,
Enable Interrupt
CONT → A
IOCR → A
R2+A → R2,
Bits 8~9 of R2 unchanged
A → R
0 → A
0 → R
R-A → A
R-A → R
R-1 → A
R-1 → R
A ∨ VR → A
A & R → A
A & R → R
A ⊕ R → A
A ⊕ R → R
A + R → A
R → A
R → R
/R → A
/R → R
R+1 → A
R+1 → R
R-1 → A, skip if zero
R-1 → R, skip if zero
R(n) → A(n-1),
R(0) → C, C → A(7)
R(n) → R(n-1),
Decimal Adjust A
Enable Interrupt
[Top of Stack] → PC
A ∨ VR → R
A + R → R
(This specification is subject to change without further notice)
OPERATION
Product Specification (V1.2) 05.27.2004
STATUS AFFECTED
None
C
None
T,P
T,P
None <Note1>
None
None
None
None
None
None <Note1>
Z,C,DC
None
Z
Z
Z,C,DC
Z,C,DC
Z
Z
Z
Z
Z
Z
Z
Z
Z,C,DC
Z,C,DC
Z
Z
Z
Z
Z
Z
None
None
C
C