EM78451AP EMC [ELAN Microelectronics Corp], EM78451AP Datasheet - Page 41

• Manufacturer Part Number: EM78451AP
• Description: 8-Bit Microcontroller
• Manufacturer: EMC [ELAN Microelectronics Corp]

Product Specification (V1.2) 05.27.2004
(This specification is subject to change without further notice)
4.8 Interrupt
The Status of RST, T, and P of STATUS Register
A RESET condition is initiated by the following events:
1. A power-on condition.
2. Watchdog timer time-out.
The values of T and P, listed in Table 7 are used to check how the processor wakes up.
Table 8 shows the events that may affect the status of T and P.
Table 7 The Values of RST, T and P After RESET
*P: Previous status before reset
Table 8 The Status of RST, T and P Being Affected by Events
*P: Previous value before reset
The EM78451 has the following interrupts.
1. TCC overflow interrupt
2. External interrupt (/INT)
3. (SPI) Serial Peripheral Interface. Transmission completed interrupt.
4. Timer1 comparator completed interrupt.
R3F is the interrupt status register, which records the interrupt request in flag bit. IOCF
is the interrupt mask register. Global interrupt is enabled by ENI instruction and is
disabled by DISI instruction. When one of the interrupts (if enabled) is generated, it will
cause the next instruction to be fetched from address 001H. Once in the interrupt
service routine the source of the interrupt can be determined by polling the flag bits in
the R3F register. The interrupt flag bit must be cleared by software before leaving the
interrupt service routine and enabling interrupts to avoid recursive interrupts.
Power on
WDT during Operating mode
WDT wake-up during SLEEP1 mode
WDT wake-up during SLEEP2 mode
Wake-Up on pin change during SLEEP2 mode
Power on
WDTC instruction
WDT time-out
SLEP instruction
Wake-Up on pin change during SLEEP2 mode
Reset Type
Event
8-Bit Microcontroller
T
P
1
1
0
1
P
T
1
0
0
0
EM78451
*P
P
P
1
1
0
P
P
P
P
1
0
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