X24645F ICMIC [IC MICROSYSTEMS], X24645F Datasheet - Page 7

• Manufacturer Part Number: X24645F
• Description: Advanced 2-Wire Serial E2PROM with Block LockTM Protection
• Manufacturer: ICMIC [IC MICROSYSTEMS]

X24645
Figure 7. Current Address Read
Figure 8. Random Read
READ OPERATIONS
Read operations are initiated in the same manner as write
operations with the exception that the R/W bit of
the slave address is set HIGH. There are three basic read
operations: current address read, random read
and sequential read.
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condition
during the ninth cycle or hold SDA HIGH during the
ninth clock cycle and then issue a stop condition.
Current Address Read
Internally the X24645 contains an address counter that
maintains the address of the last byte read, increment-
ed by one or the exact address of the last byte written.
Therefore, if the last access read was to address n, the
set HIGH, the X24645 issues an acknowledge
next read operation would access data from address
n + 1. Upon receipt of the slave address with the R/W
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
X24645
S
S
T
A
R
T
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
X24645
ADDRESS
SLAVE
S
A
R
T
A
C
K
S
T
ADDRESS n
ADDRESS
SLAVE
BYTE
7
acknowledge and by issuing a stop condition. Refer to
Figure 8 for the address, acknowledge and data
and transmits the byte. The read operation is terminated by
the master; by not responding with an acknowledge
and by issuing a stop condition. Refer to Figure 7 for the
sequence of address, acknowledge and data transfer.
Random Read
Random read operations allow the master to access any
memory location in a random manner. Prior to issuing
the slave address with the R/W bit set HIGH, the master must
first perform a “dummy” write operation.
The master issues the start condition, and the slave ad-
dress with the R/W bit set LOW, followed by the byte
address it is to read. After the word address acknowledge,
the master immediately reissues the start condition
and the slave address with the R/W bit set HIGH.
This will be followed by an acknowledge from the
X24645 and then by the data byte. The read operation is
terminated by the master; by not responding with an
transfer sequence.
A
C
K
A
C
K
S
A
R
T
S
T
ADDRESS
DATA
SLAVE
2783 ILL F11
P
A
C
K
S
T
O
P
DATA n
2783 ILL F12.1
P
O
P
S
T