H5PS5162FFR-C HYNIX [Hynix Semiconductor], H5PS5162FFR-C Datasheet - Page 17

• Manufacturer Part Number: H5PS5162FFR-C
• Description: 512Mb DDR2 SDRAM
• Manufacturer: HYNIX [Hynix Semiconductor]

Rev. 1.0 / July. 2008
For purposes of IDD testing, the following parameters are to be utilized
Detailed IDD7
The detailed timings are shown below for IDD7. Changes will be required if timing parameter changes are made to the
specification.
Legend: A = Active; RA = Read with Autoprecharge; D = Deselect
IDD7: Operating Current: All Bank Interleave Read operation
All banks are being interleaved at minimum t RC(IDD) without violating t RRD(IDD) using a burst length of 4. Control
and address bus inputs are STABLE during DESELECTs. IOUT = 0mA
Timing Patterns for 4 bank devices
-DDR2-400 3/3/3: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D (11 clocks)
-DDR2-533 3/3/3: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D (15 clocks)
-DDR2-533 4/4/4: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D (16 clocks)
-DDR2-667 4/4/4: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D (19 clocks)
-DDR2-667 5/5/5: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D (20 clocks)
-DDR2-800 5/5/5: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D D D D (23 clocks)
-DDR2-800 6/6/6: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D D D D D (24 clocks)
t RFC(IDD)-512Mb
(CL-tRCD-tRP)
t RASmax(IDD)
t RASmin(IDD)
Speed Bin
t RCD(IDD)
t RRD(IDD)
t RC(IDD)
t CK(IDD)
t RP(IDD)
CL(IDD)
5-5-5
70000
57.25
12.5
12.5
105
2.5
10
45
5
DDR2-800
6-6-6
70000
105
2.5
15
60
10
45
15
6
DDR2-667
5-5-5
70000
105
15
60
10
45
15
5
3
DDR2-533
4-4-4
70000
3.75
105
15
60
10
45
15
4
H5PS5162FFR series
DDR2-400
3-3-3
70000
105
15
55
10
40
15
3
5
Release
Units
tCK
ns
ns
ns
ns
ns
ns
ns
ns
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