H57V2622GMR-60X HYNIX [Hynix Semiconductor], H57V2622GMR-60X Datasheet
H57V2622GMR-60X
Related parts for H57V2622GMR-60X
H57V2622GMR-60X Summary of contents
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Dual Die Synchronous DRAM 256M (8Mx32bit) Hynix SDRAM This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are ...
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... Synchronous DRAM Revision History Revision No. 0.1 1.0 Rev 1.0 / Oct. 2009 Synchronous DRAM Memory 256Mbit Document Title History Initial Draft Release H57V2622GMR Series Draft Date Remark Sep. 2009 Preliminary Oct. 2009 2 ...
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... DESCRIPTION The Hynix H57V2622GMR Synchronous DRAM (Dual Die) ideally suited for the consumer memory applications which requires large memory density and high bandwidth uses Hinix’s 128Mb SDR monolithic die and has similar functional- ity. Synchronous DRAM is a type of DRAM which operates in synchronization with input clock. The Hynix Synchronous DRAM latch each control signal at the rising edge of a basic input clock (CLK) and input/output data in synchronization with the input clock (CLK) ...
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... ORDERING INFORMATION Clock Part Number Frequency H57V2622GMR-60X 166MHz H57V2622GMR-75X 133MHz H57V2622GMR-60X 166MHz H57V2622GMR-75X 133MHz Note : 1. H57V2622GMR-XXC : Normal power, Commercial Temp. (0~70℃) 2. H57V2622GMR-XXI : Normal power, Industrial Temp. (-40~85℃) 3. H57V2622GMR-XXL : Low power, Commercail Temp. (0~70℃) 4. H57V2622GMR-XXJ : Low power, Industrial Temp. (-40~85℃) Rev 1.0 / Oct. 2009 = 3 ...
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... DQ30 DQ31 NC DQM3 A3 Top A5 A6 View A8 NC CKE DQ8 VSS DQ10 DQ9 DQ12 DQ14 VDDQ VSSQ DQ15 VSS H57V2622GMR Series VDD DQ23 DQ21 VDDQ VSSQ DQ19 DQ22 DQ20 VDDQ DQ17 DQ18 VDDQ NC DQ16 VSSQ A2 DQM2 VDD A10 A0 A1 ...
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... Controls output buffers in read mode and masks input data in write mode Data Input / Output: DQ0 ~ DQ31 I/O Multiplexed data input / output pin SUPPLY Power supply SUPPLY I/O Power supply DDQ SSQ connection : These pads should be left unconnected Rev 1.0 / Oct. 2009 Synchronous DRAM Memory 256Mbit H57V2622GMR Series DESCRIPTION 6 ...
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... Synchronous DRAM Memory 256Mbit Internal Row Counter 2Mx16 Bank0~4 Row Pre Decoder Column Pre Decoder Column Add Counter Burst Counter CAS Latency Mode Register H57V2622GMR Series 2nd Die 1st Die 2Mx16 Bank0~4 Memory Cell Array Y decoerders Pipe Line Control Data Out Control DQ0 DQ31 7 ...
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... DDQ SOLDER (Commercial : TA = 0~70℃, Industrial : TA = -40~85℃) Symbol Min 3.0 DD DDQ V 2 -0.3 IL Symbol trip outref CL H57V2622GMR Series Rating - -55 ~ 125 -1.0 ~ 4.6 -1 260 10 Max Unit 3 0.3 V DDQ 0.8 V Value Unit 2 DDQ ...
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... Rev 1.0 / Oct. 2009 Synchronous DRAM Memory 256Mbit VTT = 1. 250 Ohom Output 50pF Pin (Commercial : TA = 0~70℃, Industrial : TA = -40~85℃) Symbol Min 2 H57V2622GMR Series VTT = 1. Ohom Ohom 50pF AC Output Load Circuit Symbol Min Max CI1 4.0 8.0 CI2 4.0 8.0 CI3 4.0 8.0 CI/O 3.5 6.5 Max ...
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... Specified values are measured with the output open. DD1 DD4 2. Min. of tRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II 3. H57V2622GMR-XXC : Normal, H57V2622GMR-XXL : Low Power Rev 1.0 / Oct. 2009 Synchronous DRAM Memory 256Mbit (Commercial : TA = 0~70℃, Industrial : TA = -40~85℃) ...
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... 1.5 CKS t 0.8 CKH 1.0 OLZ 2.7 OHZ3 OHZ2 & t > 1ns, then [(t +t )/2-1]ns should be added to the parameter H57V2622GMR Series 133 Unit Max Min Max 1000 7.5 1000 1000 5 1.5 - ...
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... RAS RRD t CCD t WTL t DPL t DAL t DQZ t DQM t MRD PROZ3 PROZ2 t DPE t SRE t REF after self refresh exit. Synchronous DRAM Memory 256Mbit H57V2622GMR Series 166 133 Unit Min Max Min Max 100K 42 100K ...
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... Reserved Rev 1.0 / Oct. 2009 Code 0 0 Burst Length Synchronous DRAM Memory 256Mbit H57V2622GMR Series CAS Latency BT Burst Length Burst Type A3 Burst Type 0 Sequential 1 Interleave Burst Length ...
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... Synchronous DRAM Memory 256Mbit H57V2622GMR Series A10 WE DQM ADDR / Code Row Address Col umn Col umn ...
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... H: High Level, L: Low Level, X: Don 2. Write DQM Latency is 0 CLK and Read DQM Latency is 2 CLK Rev 1.0 / Oct. 2009 CKEn Care Synchronous DRAM Memory 256Mbit H57V2622GMR Series CKEn DQM0 DQM1 DQM2 ...
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... Bank Activate Col Add. BA Write/WriteAP A10 Col Add. BA Read/ReadAP A10 Operation Synchronous DRAM Memory 256Mbit H57V2622GMR Series Action Set the Mode Register Start Auto or Self Refresh No Operation Activate the specified bank and row ILLEGAL ILLEGAL No Operation No Operation or Power Down ILLEGAL ...
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... X Precharge BA Row Add. Bank Activate BA Col Add. A10 Write/WriteAP BA Col Add. A10 Read/ReadAP Operation X X Device Deselect H57V2622GMR Series Action Notes Continue the Burst ILLEGAL 13 13 Termination Burst: Start 10 the Precharge ILLEGAL 4 Termination Burst: Start 8 Write(optional AP) Termination Burst: Start 8,9 Read(optional AP) ...
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... X X Auto or Self Refresh ILLEGAL BA X Precharge BA Row Add. Bank Activate BA Col Add. A10 Write/WriteAP BA Col Add. A10 Read/ReadAP Operation H57V2622GMR Series Action Notes ILLEGAL Operation: Bank(s) idle after t RP ILLEGAL 4,12 ILLEGAL 4,12 ILLEGAL 4,12 No Operation: Bank(s) idle after Operation: ...
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... Auto or Self Refresh ILLEGAL BA X Precharge BA Row Add. Bank Activate BA Col Add. A10 Write/WriteAP BA Col Add. A10 Read/ReadAP Operation X X Device Deselect H57V2622GMR Series Action Notes No Operation: Row Active after t DPL ILLEGAL 13 13 ILLEGAL 4,13 ILLEGAL 4,12 ILLEGAL 4,12 ILLEGAL 4,9,12 No Operation: Precharge after t ...
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... Must mask preceding data which don 11. Illegal not satisfied RRD 12. Illegal for single bank, but legal for other banks in multi-bank devices. 13. Illegal for all banks. Rev 1.0 / Oct. 2009 ' t care, BA: Bank Address, AP: Auto Precharge satisfy t . DPL Synchronous DRAM Memory 256Mbit H57V2622GMR Series 20 ...
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... CODE H57V2622GMR Series Action ADDR X INVALID Exit Self Refresh with X Device Deselect Exit Self Refresh with X No Operation X ILLEGAL X ILLEGAL X ILLEGAL X Maintain Self Refresh X INVALID X Power Down mode exit, all banks idle ...
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... Command BA0, CS RAS CAS WE BA1 H57V2622GMR Series Action ADDR Refer to operations of X the Current State Truth Table Begin Clock Suspend X next cycle Exit Clock Suspend X next cycle X Maintain Clock Suspend Notes 22 ...
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... PACKAGE INFORMATION 90 Ball FBGA, 8mm x 13mm x 1.1mm, 0.8mm pitch 8.00 ± 0.10 0.8(Typ) 0.8 6.40 BSC Bottom View 3.20 ± 0.05 Rev 1.0 / Oct. 2009 Synchronous DRAM Memory 256Mbit A1 Index Mark 4.00 0.05 ± 1.1max H57V2622GMR Series Unit [mm] 0.450 ± 0.05 0.340 ± 0.05 Side View 23 ...