T5761 ATMEL [ATMEL Corporation], T5761 Datasheet - Page 9

• Manufacturer Part Number: T5761
• Description: UHF ASK/FSK Receiver
• Manufacturer: ATMEL [ATMEL Corporation]

Bit-Check Mode
In bit-check mode the incoming data stream is examined
to distinguish between a valid signal from a correspond-
ing transmitter and signals due to noise. This is done by
subsequent time frame checks where the distances be-
tween 2 signal edges are continuously compared to a
programmable time window. The maximum count of this
edge-to-edge tests before the receiver switches to receiv-
ing mode is also programmable.
Configuring the Bit Check
Assuming a modulation scheme that contains 2 edges per
bit, two time frame checks are verifying one bit. This is
valid for Manchester, Bi-phase and most other modula-
tion schemes. The maximum count of bits to be checked
can be set to 0, 3, 6 or 9 bits via the variable N
the OPMODE register. This implies 0, 6, 12 and 18 edge
to edge checks respectively. If N
value, the receiver is less likely to switch to receiving
mode due to noise. In the presence of a valid transmitter
signal, the bit check takes less time if N
a lower value. In polling mode, the bit-check time is not
dependent on N
where 3 bits are tested successfully and the data signal is
transferred to Pin DATA.
According to figure 13, the time window for the bit check
is defined by two separate time limits. If the edge-to-edge
time t
and the upper bit-check limit T
continued. If t
T
ceiver switches to sleep mode.
For best noise immunity it is recommended to use a low
span between T
Rev. A2, 19-Oct-00
Dem_out
Lim_max
ee
is in between the lower bit-check limit T
Figure 10. Valid time window for bit check
, the bit check will be terminated and the re-
ee
Lim_min
Bit-check
is smaller than T
T
Lim_min
T
Lim_max
t
ee
and T
. Figure 12 shows an example
Lim_max
1/f
Lim_max
Sig
Bit-check
Lim_min
. This is achieved us-
Preliminary Information
, the check will be
Bit-check
is set to a higher
or t
ee
Bit-check
is set to
exceeds
Lim_min
in
ing a fixed frequency at a 50% duty cycle for the
transmitter preburst. A ‘11111...’ or a ‘10101...’ sequence
in Manchester or Bi-phase is a good choice concerning
that advice. A good compromise between receiver sensi-
tivity and susceptibility to noise is a time window of
ing pre-burst patterns that contain various edge-to-edge
time periods, the bit-check limits must be programmed
according to the required span.
The bit-check limits are determined by means of the for-
mula below.
T
T
Lim_min and Lim_max are defined by a 5-bit word each
within the LIMIT register.
Using above formulas, Lim_min and Lim_max can be de-
termined according to the required T
and T
T
(t
chapter ‘Receiving Mode’. The lower limit should be set
to Lim_min
is Lim_max = 63.
If the calculated value for Lim_min is < 19, it is recom-
mended to check 6 or 9 bits (N
switching to receiving mode due to noise.
Figures 14, 15 and 16 illustrate the bit check for the bit-
check limits Lim_min = 14 and Lim_max = 24. When
the IC is enabled, the signal processing circuits are en-
abled during T
demodulator (Dem_out) is undefined during that period.
When the bit check becomes active, the bit-check counter
is clocked with the cycle T
Figure 14 shows how the bit check proceeds if the bit-
check counter value CV_Lim is within the limits defined
by Lim_min and Lim_max at the occurrence of a signal
edge. In figure 15 the bit check fails as the value CV_lim
is lower than the limit Lim_min. The bit check also fails
if CV_Lim reaches Lim_max. This is illustrated in
figure 16.
Lim_min
Lim_max
Lim_max
DATA_L_min
25% regarding the expected edge-to-edge time t
XClk
= Lim_min
= (Lim_max –1)
is T
. The time resolution defining T
, t
XClk
10. The maximum value of the upper limit
DATA_H_min
Startup
. The minimum edge-to-edge time t
T5760 /
. The output of the ASK/ FSK
T
XClk
) is defined according to the
XClk
T
XClk
.
Bit-check
Lim_min
T5761
) to prevent
Lim_min
, T
Lim_max
9 (32)
ee
. Us-
and
ee