T5761 ATMEL [ATMEL Corporation], T5761 Datasheet - Page 16
![no-image](/images/no-image-200.jpg)
T5761
Manufacturer Part Number
T5761
Description
UHF ASK/FSK Receiver
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.T5761.pdf
(32 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Digital Noise Suppression
After a data transmission, digital noise appears on the data
output (see figure 26). To prevent that digital noise keeps
the connected C busy, it can be suppressed in two differ-
ent ways.
1.
If the bit Noise_Disable (table 9) in the OPMODE register
is set to 1 (default), the receiver changes to bit-check
mode at the end of a valid data stream. The digital noise
T5760 T5761
16 (32)
Data_out (DATA)
DATA_CLK
Data_out (DATA)
DATA_CLK
Dem_out
Data_out (DATA)
DATA_CLK
Automatic noise suppression:
Bit–check
Bit–check
mode
mode
/
Bit check ok
Bit check ok
Preburst
Preburst
Receiving mode,
data clock control
logic active
Receiving mode,
data clock control
logic active
Figure 26. Output of digital noise at the end of the data stream
’1’
Receiving mode,
data clock control
logic active
Figure 28. Occurence of a pulse at the end of the data stream
Data stream
Data
Data
Preliminary Information
Timing error
’1’
Figure 27. Automatic noise suppression
’1’
Digital Noise
(t
ee
< T
T
ee
Receiving mode,
bit check aktive
Lim_min
Bit–check
mode
OR T
is suppressed and the level at Pin DATA is High in that
case. The receiver changes back to receiving mode, if the
bit check was successful.
This way to suppress the noise is recommended if the data
stream is Manchester or Bi-phase coded and is active after
power on.
Figure 28 illustrates the behavior of the data output at the
end of a data stream. Note that if the last period of the data
stream is a high period (rising edge to falling edge), a
pulse occurs on Pin DATA. The length of the pulse
depends on the selected baud-rate range.
T
Digital Noise
Lim_max
Pulse
Bit check ok
< t
Bit check ok
ee
< T
Digital noise
Lim_min_2T
Preburst
Bit–check mode
Preburst
Receiving mode,
data clock control
logic active
Receiving mode,
data clock control
logic active
OR t
ee
Data
Data
> T
Lim_max_2T
Rev. A2, 19-Oct-00
Receiving mode,
bit check aktive
)
Digital Noise
Bit–check
mode