T5761 ATMEL [ATMEL Corporation], T5761 Datasheet - Page 15

• Manufacturer Part Number: T5761
• Description: UHF ASK/FSK Receiver
• Manufacturer: ATMEL [ATMEL Corporation]

The delay of the data clock is calculated as follows:
t
t
and Data_In. For the rising edge, t
capacitive load C
resistor R
tionally on the external voltage V
Rev. A2, 19-Oct-00
Delay
Delay1
DATA_CLK
Dem_out
Data_out (DATA)
= t
is the delay between the internal signals Data_Out
Delay1
pup
. For the falling edge, t
+ t
L
Delay2
at Pin DATA and the external pull–up
Figure 25. Timing characteristic of the data clock (falling edge of the Pin DATA)
Serial bi–directional
data line
Data_In
DATA_CLK
Data_Out
Data_Out
Serial bi–directional
data line
Data_In
DATA_CLK
Figure 24. Timing characteristic of the data clock (rising edge on Pin DATA)
’1’
Figure 23. Output of the data clock after a successful bit check
Receiving mode,
bit check active
Bit check ok
X
(see figures 24, 25 and
Delay1
Delay1
Preliminary Information
’1’
V
V
Il
Ih
= 0,65 * V S
= 0,35 * V S
depends on the
depends addi-
’1’
V
X
’1’
t
Delay1
t
t
Delay
Delay1
t
Delay
’1’
t
Delay2
32). When the level of Data_In is equal to the level of
Data_Out, the data clock is issued after an additional
delay t
Note that the capacitive load at Pin DATA is limited. If the
maximum tolerated capacitive load at Pin DATA is ex-
ceeded, the data clock disappears (see chapter ’Data
Interface’).
t
P_Data_Clk
t
Delay2
t
Data
P_Data_Clk
Start bit
’0’
Delay2
V
V
V
X
Ih
Il
= 0,35 * VS
= 0,65 * VS
Receiving mode,
data clock control
logic active
’1’
.
T5760 /
’1’
’0’
’1’
T5761
’0’
15 (32)