ST70137TQFP STMICROELECTRONICS [STMicroelectronics], ST70137TQFP Datasheet - Page 9

• Manufacturer Part Number: ST70137TQFP
• Description: UNICORNTM PCI & USB CONTROLLERLESS ADSL DMT TRANSCEIVER
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST70137
PIN DESCRIPTION
9/22
PCI INTERFACE
PCI_CLK
PCI_RSTN
PCI_REQN
PCI_GNTN
PCI_AD[31:0]
Signal Name
Direction Init Status
I/O
O
I
I
I
H
-
I
I
I
Polarity
L
L
L
-
-
PCI Clock. (33 MHz)
The rising edge of this signal is the reference upon which
all the other PCI signals are based except for PCI_RSTN
and PCI_INTAN. The maximum PCI_CLK frequency for
ST70137 is 33MHz and the minimum is DC.
PCI Reset
Reset bring ST70137 in a known state:
- All PCI bus output signal tri-stated
- All open drain signals floated
- All registers set to their factory defaults
- All FIFOs emptied
- GPIO signals tri-stated
- Sachem Macrocell initialized
- Clock of Adsl_Up stopped
- AFE set in Power down mode
PCI Request
This signal is sourced by an agent wishing to become a
bus master. It is a point to point signal and each master
has its own PCI_REQN.
PCI Grant
The PCI_GNTN signal is a dedicated, point-to-point signal
provided to each potential bus master and signifies that
access to the bus has been granted.
PCI Multiplexed Address/Data Bus
Address and data are multiplexed on the same PCI bus
pins. A PCI bus transaction consists of an address phase
followed by the one or more data phase. An address
phase occurs on the PCLK cycle in which PCI_FRAMEN
is asserted. A data phase occurs on PCLK cycles in which
PCI_IRDYN and PCI_TRDYN are both asserted.
Signal Description