ST70137TQFP STMICROELECTRONICS [STMicroelectronics], ST70137TQFP Datasheet - Page 11

• Manufacturer Part Number: ST70137TQFP
• Description: UNICORNTM PCI & USB CONTROLLERLESS ADSL DMT TRANSCEIVER
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST70137
PIN DESCRIPTION (continued)
11/22
PCI_TRDYN
PCI_PERRN
PCI_SERRN
PCI_INTAN
PCI_PMEN
PCI_STOPN
USB INTERFACE
DPLUS
DMINUS
MISCELLANEOUS INTERFACE
GPIO[3:0]
CFG_MEM_SEL
USB_PCIN_sel
VAUX_D / USB_SP
Signal Name
Direction Init Status
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
I
I
I
Z
Z
Z
I
I
I
I
I
I
I
I
I
Polarity
L
L
L
L
L
L
+
-
-
-
-
-
PCI Target Ready
This signal is driven by the select target to indicate the tar-
get is able to complete the current data phase. During
read transactions, it indicates PCI_AD[] contains valid
data. Wait states occur until both PCI_TRDYN and
PCI_IRDYN are asserted togheter.
PCI Parity Error
Only for reporting data parity errors for all bus transactions
except for special cycles. It is driven by the agent receiving
data two clock cycles after the parity was detected as an
error. This signal is driven inactive (high) for one clock
cycle prior to returning to the tri-state condition.
PCI System Error
Used to report address and data parity errors on special
cycle commands and any other error condition having a
catastrophic system impact.
PCI Interrupt A
This signal is defined as optional and level sensitive. Driv-
ing it low will interrupt to the host. The PCI_INTAN inter-
rupt is to be used for any single function device requiring
an interrupt capability.
PCI Power Management Event
This signal is used to indicate that a power management
event has been detected. The PCI_PMEN signal is asyn-
chronous with respect to the PCI clock; it is set (if
enabled) by the low to high transition of the ACTD signal.
PCI Stop
This signal indicates the current target is requesting the
master to stop the current transaction.
Differential positive USB data input/output.
Differential negative USB data input/output.
General Purpose I/O Bus
These signals are controlled by internal registers located
inside ADSL uP block. At the Power-up, Hardware or
Software Reset the input direction is chosen.
Select Internal [1] or External [0] PCI/USB configuration
memory.
Select PCI [0] or USB [1] Interface
Selecting USB interface and if all Test Pins are set to
default value, all the PCI Pads are deactivated. The
power supply for this section can be not provided. The
PCI section is frozen.
Selecting PCI interface the DMINUS and DPLUS has to be
set to the low level (reset mode). The PLL is in power down
and no any clock will be provided to the USB section.
VAUX Detect when USB_PCIN_sel = [0] or USB SELF
POWERED when USB_PCIN_sel = [1].
Signal Description