WJCE6353SL9G5882170 INTEL [Intel Corporation], WJCE6353SL9G5882170 Datasheet - Page 25

• Manufacturer Part Number: WJCE6353SL9G5882170
• Description: Nordig Unified DVB-T COFDM Terrestrial Demodulator for PC-TV and Hand-held Digital TV (DTV)
• Manufacturer: INTEL [Intel Corporation]

4.4.1.5
•
•
•
•
•
•
On the printed circuit board, the tracks to the crystal and capacitors must be made as short as possible.
Other signal tracks must not be allowed to cross through this area. The component tracks should preferably
be ringed by a ground track connected to the chip ground (0 V) on adjacent pins either side of the crystal
pins. It is also advisable to provide a ground plane for the circuit to reduce noise.
External clock signals, applied to XTI and/or XTO, must not exceed the cell supply limits (i.e., 0V and CVDD)
and current into or out of XTI and/or XTO must be limited to less than 10mA to avoid damaging the cell’s
amplitude clamping circuit.
An external, DC coupled, single ended square wave clock signal may be applied to XTI if OSCMODE = 0. To
limit the current taken from the signal source a resistor should be placed between the clock source and XTI.
The recommended value for this series resistor is 470 Ω for a clock signal switching between 0 V and
CVDD. The current the clock source needs to source/sink is then <1.9 mA. The XTO pin must be left
unconnected in this configuration.
AC coupling of a single ended external clock to XTI, with OSCMODE = 0, is not recommended. The duty
cycle of the OSCOUT signal cannot be guaranteed in such a configuration.
AC coupling of a single ended external clock to XTI, with OSCMODE = 1, is possible. It is recommended that
the circuit shown in Figure 11 be used to correctly bias the oscillator inputs: The common-mode voltage VCM
for XTI and XTO, (set by the 36 kΩ and 22 kΩ resistors) must be 800 mV < VCM < CVDD and the amplitude
Vpp of the clock signal must be >100 mV.
External, differential clock signals may be applied to XTI and XTO if OSCMODE = 1. The common-mode
voltage VCM for the differential clock signals must be 800 mV < VCM < CVDD, and the peak-to-peak signal
amplitude Vpp must be >100 mV. It is recommended that differential clock signals have VCM = 1.0V. For
Vpp > 400 mV a resistor of >390 Ω in series with XTI or XTO may be required to limit the current taken from
or supplied to the clock sources.
Oscillator/Clock Application Notes
External clock
Figure 11 - External Clocking via AC Coupling
10nF
XTI
100k
Intel Corporation
CE6353
25
10nF
XTO
22k
36k
Vdd
OSCMODE
Data Sheet