WJCE6353SL9G5882170 INTEL [Intel Corporation], WJCE6353SL9G5882170 Datasheet - Page 17

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WJCE6353SL9G5882170

Manufacturer Part Number
WJCE6353SL9G5882170
Description
Nordig Unified DVB-T COFDM Terrestrial Demodulator for PC-TV and Hand-held Digital TV (DTV)
Manufacturer
INTEL [Intel Corporation]
Datasheet
CLK clock frequency (Primary)
Bus free time between a STOP and START condition.
Hold time (repeated) START condition.
LOW period of CLK clock.
HIGH period of CLK clock.
Set-up time for a repeated START condition.
Data hold time (when input).
Data set-up time
Rise time of both CLK and DATA signals.
Fall time of both CLK and DATA signals, (100 pF to ground).
Set-up time for a STOP condition.
1. If operating with an external 4 MHz clock, the serial clock frequency is reduced to 100 kHz maximum.
2. The rise time depends on the external bus pull up resistor. Loading prevents full speed operation.
Parameter
Table 3 - Timing of 2-Wire Bus
Intel Corporation
CE6353
17
f
t
t
t
t
t
t
t
t
t
t
CLK
BUFF
HD;STA
LOW
HIGH
SU;STA
HD;DAT
SU;DAT
R
F
SU;STO
Symbol
1300
Min.
200
200
600
200
100
100
200
20
0
Value
note
400
Max.
1
Data Sheet
2
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit

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