WJCE6353SL9G5882170 INTEL [Intel Corporation], WJCE6353SL9G5882170 Datasheet - Page 19

• Manufacturer Part Number: WJCE6353SL9G5882170
• Description: Nordig Unified DVB-T COFDM Terrestrial Demodulator for PC-TV and Hand-held Digital TV (DTV)
• Manufacturer: INTEL [Intel Corporation]

3.2.2
The MPEGEN bit in the CONFIG register must be set low to enable the MPEG data. The maximum movement in
the packet synchronization byte position is limited to ±1 output clock period. MOCLK will be a continuously running
clock once symbol lock has been achieved, and is derived from the symbol clock. MOCLK is shown in Figure 7 with
MOCLKINV = ‘1’, the default state, see register 0x50.
All output data and signals (MDO[7:0], MOSTRT, MOVAL & BKERR) change on the negative edge of MOCLK
(MOCLKINV = 1) to present stable data and signals on the positive edge of the clock.
A complete packet is output on MDO[7:0] on 188 consecutive clocks and the MDO[7:0] pins will remain low during
the inter-packet gaps. MOSTRT goes high for the first byte clock of a packet. MOVAL goes high on the first byte of
a packet and remains high until the last byte has been clocked out. BKERR goes low on the first byte of a packet
where uncorrectable bytes are detected and will remain low until the last byte has been clocked out.
3.2.3
Maximum delay conditions: VDD = 3.0V, CVDD = 1.62V, Tamb = 80
Minimum delay conditions: VDD = 3.6V, CVDD = 1.98V, Tamb = -10
MOCLK frequency = 45.06 MHz.
MPEG Data Output Signals
MPEG Output Timing
MOCLKINV=1
MOCLK
MDO7:0
MOSTRT
MOVAL
BKERR
1st byte packet n
Figure 7 - MPEG Output Data Waveforms
Tp
188 byte packet n
Intel Corporation
CE6353
19
o
o
C, Output load = 10pF.
C, Output load = 10pF.
Ti
1st byte packet n+1
Data Sheet