K6R1004C1C SAMSUNG [Samsung semiconductor], K6R1004C1C Datasheet - Page 7

• Manufacturer Part Number: K6R1004C1C
• Description: 256Kx4 Bit (with OE) High-Speed CMOS Static RAM(5.0V Operating).
• Manufacturer: SAMSUNG [Samsung semiconductor]

K6R1004C1C-C/C-L, K6R1004C1C-I/C-P
FUNCTIONAL DESCRIPTION
* X means Don t Care.
TIMING WAVEFORM OF WRITE CYCLE(3)
CS
H
L
L
L
Address
CS
WE
Data in
Data out
NOTES(WRITE CYCLE)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ;
3. t
4. t
5. t
6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.
9. Dout is the read data of the new address.
10.When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be
WE
A write ends at the earliest transition CS going high or WE going high. t
write.
of the output must not be applied because bus contention can occur.
applied.
CW
AS
WR
X
H
H
L
is measured from the address valid to the beginning of write.
is measured from the later of CS going low to end of write.
is measured from the end of write to the address change. t
High-Z
High-Z
OE
X*
H
X
L
t
AS(4)
Output Disable
t
Not Select
(CS=Controlled)
LZ
Mode
Read
Write
- 7 -
t
WHZ(6)
t
AW
t
CW(3)
t
WR
WC
t
WP(2)
applied in case a write ends as CS or WE going high.
WP
I/O Pin
High-Z
High-Z
D
is measured from the beginning of write to the end of
D
OUT
IN
Valid Data
t
DW
PRELIMINARY
t
WR(5)
t
DH
CMOS SRAM
High-Z(8)
Supply Current
PRELIMINARY
High-Z
I
SB
September 2001
I
I
I
, I
CC
CC
CC
SB1
Revision 3.0