K7I163682B_06 SAMSUNG [Samsung semiconductor], K7I163682B_06 Datasheet - Page 5

• Manufacturer Part Number: K7I163682B_06
• Description: 512Kx36 & 1Mx18 DDRII CIO b2 SRAM
• Manufacturer: SAMSUNG [Samsung semiconductor]

K7I163682B
K7I161882B
PIN CONFIGURATIONS
Notes: 1. * Checked No Connect(NC) pins are reserved for higher density address, i.e. 2A for 72Mb.
PIN NAME
Notes: 1. C, C, K or K cannot be set to V
BW
SYMBOL
A
B
C
D
G
H
K
M
N
R
CQ, CQ
DQ0-17
E
F
L
P
J
V
V
TMS
TDO
C, C
TCK
K, K
SA0
R/W
Doff
V
V
TDI
2. When ZQ pin is directly connected to V
NC
SA
0
ZQ
2. BW
LD
3. Not connected to chip pad internally.
DDQ
REF
, BW
DD
SS
0
1
TDO
Doff
CQ
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
controls write to DQ0:DQ8 and BW
1
2A,7A,10A,1B,3B,5B,9B,10B,1C,2C,3C,9C,11C,1D,2D,9D,10D,
4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M-8M,4N,8N
3A,9A,4B,8B,5C,7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R
NC
2B,11B,10C,3D,3E,11E,2F,11F,3G,10J,3K,11K,2L,11L
1M,2M,3M,9M,11M,1N,2N,9N,10N,11N,1P,2P,9P,10P
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
DQ12
DQ15
11D,1E,2E,9E,10E,1F,3F,9F,10F,1G,2G,9G,10G,11G
DQ9
V
TCK
NC
NC
NC
NC
NC
NC
NC
NC
NC
REF
2
/
SA*
1J,2J,3J,9J,11J,1K,2K,9K,10K,1L,3L,9L,10L
5F,7F,5G,7G,5H,7H,5J,7J,5K,7K
DQ10
DQ13
DQ14
DQ16
DQ17
DQ11
(TOP VIEW) K7I161882B(1Mx18)
V
SA
NC
NC
NC
NC
NC
NC
SA
DDQ
REF
3
voltage.
PIN NUMBERS
10M,3N,3P,11P
DD
1
output impedance is set to minimum value and it cannot be connected to ground or left unconnected.
11A, 1A
2H,10H
6B, 6A
7B, 5A
6P, 6R
V
V
V
V
V
V
V
controls write to DQ9:DQ17.
R/W
V
V
V
V
SA
SA
SA
11H
10R
11R
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
1H
6C
4A
8A
2R
1R
4
SS
SS
SS
SS
BW
V
V
V
V
V
V
V
V
V
NC
SA
SA
SA
SA
5
SS
SS
DD
DD
DD
DD
DD
SS
SS
1
512Kx36 & 1Mx18 DDRII CIO b2 SRAM
- 5 -
SA0
V
V
V
V
V
V
V
V
V
SA
K
C
C
6
K
SS
SS
SS
SS
SS
SS
SS
SS
SS
BW
V
V
V
V
V
V
V
V
V
NC
SA
SA
SA
SA
7
DD
DD
DD
DD
DD
SS
SS
SS
SS
0
Block Write Control Pin,active when low
Output Driver Impedance Control Input
Output Power Supply ( 1.5V or 1.8V )
Read, Write Control Pin, Read active
sequence is to be defined when low
Synchronous Load Pin, bus Cycle
Burst Count Address Inputs
Input Clock for Output Data
V
V
V
V
V
V
V
V
V
V
V
Input Reference Voltage
JTAG Test Mode Select
LD
SA
SA
SA
JTAG Test Data Output
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
Power Supply ( 1.8 V )
DLL Disable when low
8
JTAG Test Data Input
SS
SS
SS
SS
Data Inputs Outputs
Output Echo Clock
JTAG Test Clock
DESCRIPTION
Address Inputs
No Connect
Input Clock
when high
Ground
V
Rev. 5.0 July 2006
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
SA
SA
DDQ
9
NC/SA*
V
TMS
DQ7
DQ4
DQ1
NC
NC
NC
NC
NC
NC
NC
NC
NC
10
REF
DQ8
DQ6
DQ5
DQ3
DQ2
DQ0
TDI
NOTE
CQ
NC
NC
NC
NC
NC
NC
ZQ
11
1
2
3