K7I163682B_06 SAMSUNG [Samsung semiconductor], K7I163682B_06 Datasheet - Page 17

• Manufacturer Part Number: K7I163682B_06
• Description: 512Kx36 & 1Mx18 DDRII CIO b2 SRAM
• Manufacturer: SAMSUNG [Samsung semiconductor]

K7I163682B
K7I161882B
JTAG DC OPERATING CONDITIONS
Note: 1. The input level of SRAM pin is to follow the SRAM DC specification
JTAG AC TEST CONDITIONS
Note: 1. See SRAM AC test output load on page 11.
JTAG AC Characteristics
JTAG TIMING DIAGRAM
Power Supply Voltage
Input High Level
Input Low Level
Output High Voltage(I
Output Low Voltage(I
Input High/Low Level
Input Rise/Fall Time
Input and Output Timing Reference Level
TCK Cycle Time
TCK High Pulse Width
TCK Low Pulse Width
TMS Input Setup Time
TMS Input Hold Time
TDI Input Setup Time
TDI Input Hold Time
SRAM Input Setup Time
SRAM Input Hold Time
Clock Low to Output Valid
(SRAM)
TMS
PI
TDO
TCK
TDI
Parameter
Parameter
Parameter
OL
OH
=2mA)
=-2mA)
t
CHCH
t
CLQV
Symbol
Symbol
V
TR/TF
V
V
V
V
V
IH
OH
DD
OL
IH
IL
/V
t
t
t
Symbol
DVCH
MVCH
SVCH
IL
t
t
t
t
t
t
t
t
t
t
512Kx36 & 1Mx18 DDRII CIO b2 SRAM
CHCH
MVCH
CHMX
DVCH
CHDX
SVCH
CHSX
CHCL
CLCH
CLQV
- 17 -
.
Min
-0.3
V
1.7
1.3
1.4
SS
t
t
t
CHMX
CHDX
CHSX
Min
50
20
20
5
5
5
5
5
5
0
t
CHCL
1.8/0.0
1.0/1.0
Typ
Min
1.8
0.9
-
-
-
-
Max
10
-
-
-
-
-
-
-
-
-
V
DD
Max
V
1.9
0.5
0.4
DD
+0.3
t
Rev. 5.0 July 2006
CLCH
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
Unit
ns
V
V
V
V
V
V
V
Note
Note
Note
1