K7I161882B-FC16 SAMSUNG [Samsung semiconductor], K7I161882B-FC16 Datasheet - Page 3

• Manufacturer Part Number: K7I161882B-FC16
• Description: 512Kx36-bit, 1Mx18-bit DDRII CIO b2 SRAM
• Manufacturer: SAMSUNG [Samsung semiconductor]

K7I163682B
K7I161882B
PIN CONFIGURATIONS
Notes : 1. * Checked No Connect(NC) pins are reserved for higher density address, i.e. 10A for 72Mb, 2A for 144Mb .
PIN NAME
Notes: 1. C, C, K or K cannot be set to V
BW
G
M
A
B
C
D
E
H
K
N
P
R
F
J
L
0
, BW
2. When ZQ pin is directly connected to V
3. Not connected to chip pad internally.
SYMBOL
2. BW
CQ, CQ
DQ0-35
V
V
TMS
TDO
K, K
C, C
SA0
R/W
TCK
Doff
V
V
TDI
SA
ZQ
NC
LD
1,
DDQ
REF
DD
SS
BW
TDO
Doff
0
CQ
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
1
controls write to DQ0:DQ8, BW
2
, BW
3
V
DQ27
DQ29
DQ30
DQ31
DQ33
DQ35
SS/
V
TCK
NC
NC
NC
NC
NC
NC
REF
2
SA*
2B,3B,11B,3C,10C,11C,2D,3D,11D,3E,10E,11E,2F,3F
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
2A,10A,4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,
9A,4B,8B,5C,7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R
11F,2G,3G,11G,3J,10J,11J,3K,10K,11K,2L,3L,11L
3A,1B,9B,10B,1C,2C,9C,1D,9D,10D,1E,2E,9E,
1L,9L,10L,1M,2M,9M,1N,9N,10N,1P,2P,9P
1F,9F,10F,1G,9G,10G,1J,2J,9J,1K,2K,9K
DQ18
DQ28
DQ19
DQ20
DQ21
DQ22
DQ32
DQ23
DQ24
DQ34
DQ25
DQ26
V
(TOP VIEW)
3M,10M,11M,2N,3N,11N,3P,10P,11P
NC
SA
DDQ
REF
3
5F,7F,5G,7G,5H,7H,5J,7J,5K,7K
voltage.
1
DD
controls write to DQ9:DQ17, BW
output impedance is set to minimum value and it cannot be connected to ground or left unconnected.
PIN NUMBERS
V
V
V
V
V
V
V
4M-8M,4N,8N
R/W
V
V
V
V
7B,7A,5A,5B
SA
SA
SA
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
4
SS
SS
SS
SS
11A, 1A
2H,10H
6B, 6A
6P, 6R
11H
10R
11R
K7I163682B(512Kx36)
1H
6C
2R
1R
4A
8A
BW
BW
V
V
V
V
V
V
V
V
V
SA
SA
SA
SA
5
SS
SS
DD
DD
DD
DD
DD
SS
SS
2
3
512Kx36 & 1Mx18 DDRII CIO b2 SRAM
- 3 -
SA0
V
V
V
V
V
V
V
V
V
SA
K
K
C
C
6
SS
SS
SS
SS
SS
SS
SS
SS
SS
2
controls write to DQ18:DQ26 and BW
BW
BW
V
V
V
V
V
V
V
V
V
SA
SA
SA
SA
7
DD
DD
DD
DD
DD
SS
SS
SS
SS
1
0
Block Write Control Pin,active when low
Output Driver Impedance Control Input
Output Power Supply ( 1.5V or 1.8V )
Read, Write Control Pin, Read active
sequence is to be defined when low
Synchronous Load Pin, bus Cycle
V
V
V
V
V
V
V
Burst Count Address Inputs
Input Clock for Output Data
V
V
V
V
LD
SA
SA
SA
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
Input Reference Voltage
8
JTAG Test Mode Select
SS
SS
SS
SS
JTAG Test Data Output
Power Supply ( 1.8 V )
DLL Disable when low
JTAG Test Data Input
Data Inputs Outputs
Output Echo Clock
JTAG Test Clock
DESCRIPTION
Address Inputs
No Connect
Input Clock
when high
Ground
V
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
SA
SA
DDQ
9
3
controls write to DQ27:DQ35.
V
DQ17
DQ15
DQ13
DQ12
DQ11
SS/
V
DQ9
TMS
NC
NC
NC
NC
NC
NC
10
REF
SA*
July. 2004
DQ16
DQ14
DQ10
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
Rev 3.1
CQ
TDI
ZQ
NOTE
11
1
2
3