S5935TFC AMCC [Applied Micro Circuits Corporation], S5935TFC Datasheet - Page 126

• Manufacturer Part Number: S5935TFC
• Description: PCI Product
• Manufacturer: AMCC [Applied Micro Circuits Corporation]

S5935 – PCI Product
MAILBOX OVERVIEW
The S5935 has eight 32-bit mailbox registers. The
mailboxes are useful for passing command and status
information between the Add-On and the PCI bus. The
PCI interface has four incoming mailboxes (Add-On to
PCI) and four outgoing mailboxes (PCI to Add-On).
The Add-On interface has four incoming mailboxes
(PCI to Add-On) and four outgoing mailboxes (Add-On
to PCI). The PCI incoming and Add-On outgoing mail-
boxes are the same, internally. The Add-On incoming
and PCI outgoing mailboxes are also the same,
internally.
The mailbox status may be monitored in two ways.
The PCI and Add-On interfaces each have a mailbox
status register to indicate the empty/full status of bytes
within the mailboxes. The mailboxes may also be con-
figured to generate interrupts to the PCI and/or Add-
Figure 70. Block Diagram - PCI to Add-On Mailbox Register
Figure 71. Block Diagram - Add-On to PCI Mailbox Register
126
DS1527
PCI BUS
"OUTGOING MAILBOX"
PCI BUS
"INCOMING MAILBOX"
PCI READ PULSE
LOAD ENABLE
"O"
MAILBOX
INTERLOCK
QD
FULL
OUTPUT
LATCH
EMPTY/FULL FF
D
REGISTER
MAILBOX
D
EN
S
Q
Q
SELECTED READ ENABLE
"INCOMING
MAILBOX"
SELECTED
READ PULSE
ADD-ON
SELECT
BUS
"INCOMING
MAILBOX"
SELECT
MAILBOX
PCI
FULL
EMPTY/FULL FF
Q
INTERLOCK
On interface. One outgoing and one incoming mailbox
on each interface can be configured to generate
interrupts.
FUNCTIONAL DESCRIPTION
Figure 1 shows a block diagram of the PCI to Add-On
mailbox registers. Add-On incoming mailbox read
accesses pass through an output interlock latch. This
prevents a PCI bus write to a PCI outgoing mailbox
from corrupting data being read by the Add-On. Figure
2 shows a block diagram of the Add-On to PCI mailbox
registers. PCI incoming mailbox reads also pass
through an interlocking mechanism. This prevents an
Add-On write to an outgoing mailbox from corrupting
data being read by the PCI bus. The following sections
describe the mailbox flag functionality and the mailbox
interrupt capabilities.
S
D
EN
OUTPUT
READ ENABLE
LATCH
ADD-ON WRITE PULSE
D
Q
REGISTER
MAILBOX
QD
"O"
OUTPUT
EN
DRIVER
DECODE OF
REGISTER
ADR[6:2]
BE[3:0]#
Revision 1.02 – June 27, 2006
SELECT#
"INCOMING MAILBOX"
ADD-ON
ADD-ON
AMCC Confidential and Proprietary
"OUTGOING
BUS
RD#
MAILBOX"
ADD-ON
WR#
SELECT#
BUS
Data Book