LH540203D SHARP [Sharp Electrionic Components], LH540203D Datasheet - Page 2

• Manufacturer Part Number: LH540203D
• Description: CMOS 2048X9 ASYNCHRONOUS FIFO
• Manufacturer: SHARP [Sharp Electrionic Components]

FUNCTIONAL DESCRIPTION (cont’d)
LH540203
port in precisely the same order that they were written in
at its input port; that is, according to a First-In, First Out
(FIFO) queue discipline. Since the addressing sequence
for a FIFO device’s memory is internally predefined, no
external addressing information is required for the opera-
tion of the LH540203 device.
both larger sizes and smaller sizes of industry-standard
nine-bit asynchronous FIFOs. The only change is in the
number of internally-stored data words implied by the
states of the Full Flag and the Half-Full Flag.
FIFO-memory-array read-address pointer to be set back
to zero, to point to the LH540203’s first physical memory
location, without affecting the internal FIFO-memory-
array write-address pointer. Thus, the Retransmit control
signal provides a mechanism whereby a block of data,
delimited by the zero physical address and the current
write-address-pointer value, may be read out repeatedly
an arbitrary number of times. The only restrictions are that
neither the read-address pointer nor the write-address
pointer may ‘wrap around’ during this entire process, i.e.,
advance past physical location zero after traversing the
entire memory. The retransmit facility is not available
when an LH540203 is operating in a depth-expanded
configuration.
2
Data words are read out from the LH540203’s output
Drop-in-replacement compatibility is maintained with
The Retransmit (RT) control signal causes the internal
RS
W
CONTROL
RESET
LOGIC
INPUT
PORT
Figure 3. LH540203 Block Diagram
POINTER
WRITE
FL/RT
XI
DATA OUTPUTS
DATA INPUTS
DUAL-PORT
EXPANSION
2048 x 9
D
ARRAY
Q
LOGIC
. . .
LOGIC
RAM
FLAG
0
0
- D
- Q
8
8
to an initial state, empty and ready to be filled. An
LH540203 should be reset during every system power-up
sequence. A reset operation causes the internal FIFO-
memory-array write-address pointer, as well as the read-
address pointer, to be set back to zero, to point to the
LH540203’s first physical memory location. Any informa-
tion which previously had been stored within the
LH540203 is not recoverable after a reset operation.
mented by using the Expansion In (XI) input signal and
the Expansion Out (XO/HF) output signal. This allows a
deeper ‘effective FIFO’ to be implemented by using two
or more LH540203 devices, without incurring additional
latency (‘fallthrough’ or ‘bubblethrough’) delays, and with-
out the necessity of storing and retrieving any given data
word more than once. In this cascaded operating mode,
one LH540203 device must be designated as the ‘first-
load’ or ‘master’ device, by grounding its First-Load
(FL/RT) control input; the remaining LH540203 devices
are designated as ‘slaves,’ by tying their FL/RT inputs
HIGH. Because of the need to share control signals on
pins, the Half-Full Flag and the retransmission capability
are not available for either ‘master’ or ‘slave’ LH540203
devices operating in cascaded mode.
The Reset (RS) control signal returns the LH540203
A cascading (depth-expansion) scheme may be imple-
POINTER
XO/HF
EF
FF
READ
CMOS 2048
CONTROL
OUTPUT
PORT
9 Asynchronous FIFO
R
540203-1