LH540203D SHARP [Sharp Electrionic Components], LH540203D Datasheet

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LH540203 FEATURES Fast Access Times: 15/20/25/35/50 ns Fast-Fall-Through Time Architecture Based on CMOS Dual-Port SRAM Technology Input Port and Output Port Have Entirely Independent Timing Expandable in Width and Depth Full, Half-Full, and Empty Status Flags Data Retransmission Capability TTL-Compatible ...

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LH540203 FUNCTIONAL DESCRIPTION (cont’d) Data words are read out from the LH540203’s output port in precisely the same order that they were written in at its input port; that is, according to a First-In, First Out (FIFO) queue discipline. Since ...

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CMOS 2048 9 Asynchronous FIFO PIN DESCRIPTIONS 1 PIN PIN TYPE DESCRIPTION D – D Input Data Bus – Q Output Data Bus O Write Request I R Read Request I EF Empty ...

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LH540203 OPERATIONAL DESCRIPTION (cont’d) Retransmit The FIFO can be made to reread previously-read data by means of the Retransmit function. A retransmit opera- tion is initiated by pulsing the RT input LOW. Both R and W must be deasserted (HIGH) ...

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CMOS 2048 9 Asynchronous FIFO OPERATIONAL MODES Standalone Configuration When depth cascading is not required for a given application, the LH540203 is placed in standalone mode by tying the Expansion In input (XI) to ground. This input is internally sampled ...

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LH540203 OPERATIONAL MODES (cont’d) Depth Cascading Depth cascading is implemented by configuring the required number of LH540203s in depth-cascaded mode. In this arrangement, the FIFOs are connected in a circular fashion, with the Expansion Out output (XO) of each device ...

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CMOS 2048 9 Asynchronous FIFO OPERATIONAL MODES (cont’d) Compound FIFO Expansion A combination of word-width expansion and depth cascading may be implemented easily by operating groups of depth-cascaded FIFOs in parallel. Bidirectional FIFO Operation Bidirectional data buffering between two systems ...

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LH540203 ABSOLUTE MAXIMUM RATINGS PARAMETER Supply Voltage to V Potential SS Signal Pin Voltage to V Potential Output Current Storage Temperature Range Power Dissipation (Package Limit) DC Voltage Applied to Outputs In High-Z State NOTES: 1. Stresses ...

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CMOS 2048 9 Asynchronous FIFO AC TEST CONDITIONS PARAMETER Input Pulse Levels Input Rise and Fall Times (10% to 90%) Input Timing Reference Levels Output Reference Levels Output Load, Timing Tests 1,2 CAPACITANCE PARAMETER C (Input Capacitance (Output ...

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LH540203 AC ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER t Read Cycle Time RC t Access Time A t Read Recovery Time Read Pulse Width RPW t Data Bus Active from Read LOW RLZ t Data Bus Active from Write ...

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CMOS 2048 9 Asynchronous FIFO TIMING DIAGRAMS RS R,W EF FF,HF NOTES RSC RS RSR 2. W and R V around the rising edge of RS The Data Out pins (D ...

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LH540203 TIMING DIAGRAMS (cont’d) LAST WRITE Figure 12. Full Flag From Last Write to First Read LAST READ NOTE: The Data Out pins ( are forced into high-impedance ...

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CMOS 2048 9 Asynchronous FIFO TIMING DIAGRAMS (cont’ NOTES RPE RPW Effective Read Pulse Width after Empty Flag HIGH. RPE ...

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LH540203 TIMING DIAGRAMS (cont’ NOTES RPE RPW Effective Read Pulse Width after Empty Flag HIGH. RPE 3. The Data Out pins ( are forced into a 0 ...

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CMOS 2048 9 Asynchronous FIFO TIMING DIAGRAMS (cont’d) RT R,W NOTES RTC RT RTR 2. FF, HF, and EF may change state during retransmit; but they will become valid RTC ...

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LH540203 PACKAGE DIAGRAMS 28DIP (DIP28-W-300) 34.80 [1.370] 34.54 [1.360] 2.54 [0.100] 0.53 [0.021] TYP. 0.38 [0.015] MAXIMUM LIMIT DIMENSIONS IN MM [INCHES] MINIMUM LIMIT 28SOJ (SOJ28-P-300 18.7 [0.736] 18.3 [0.720] 0.53 [0.021] 0.33 [0.013] 1.27 [0.050] TYP. MAXIMUM ...

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CMOS 2048 9 Asynchronous FIFO 32PLCC (PLCC32-P-R450) 15.11 [0.595] 14.86 [0.585] 14.05 [0.553] 13.89 [0.547] 3.56 [0.140] 3.12 [0.123] 0.10 [0.004] MAXIMUM LIMIT DIMENSIONS IN MM (INCHES) MINIMUM LIMIT ORDERING INFORMATION LH540203 X Device Type Package * Contact a Sharp ...