HI-6010C HOLTIC [Holt Integrated Circuits], HI-6010C Datasheet - Page 3

• Manufacturer Part Number: HI-6010C
• Description: ARINC 429 TRANSMITTER/RECEIVER FOR 8 BIT BUS
• Manufacturer: HOLTIC [Holt Integrated Circuits]

receiver is not programmable to the 32 bit "extended buffer"
mode nor to the label recognition mode.
receiver:
When MR is a 1, the control word is set to 0X10 0101 (CR7 -
CR0). For the receiver this sets up 8 bit mode with the
receiver and parity enabled. MR also initializes the registers
and logic. The first ARINC reception will only occur
word gap.
In 8 bit mode, this pin goes high whenever 8 bits are received
without error. In 32 bit mode this pin goes high after all 32 bits
are received with no error. This flag may be inhibited for one
ARINC word if CR3 is programmed to 1. This flag is also
inhibited in label recognition if the incoming ARINC label does
notmatch one of the stored 8 labels.
This pin must have a clock applied that is 4X the desired
receive frequency.
In 8 bit mode, this pin flags the first character (byte) received.
In 32 bit mode, this pin goes high for a valid 32 bit word. The
pin is not affected by CR3 programming.
CONTROL PROGRAM PIN 5
BIT NAME
CR3*
* CR3 will be automatically reset to 0 after being programmed
to a 1 at the completion of an ARINC word reception. This
allows a software label recognition different from the automatic
option available.
CR1
CR2
CR4
CR5
CR7
VALUE
X
X
0
0
1
0
1
0
1
0
1
1
0
1
0
1
VALUE
X
X
X
X
X
X
0
1
1
0
0
1
1
0
1
1
PIN 8 - RXRDY
PIN 12 - RXC
PIN 13 - FCR
PIN 6 - MR
No action
No action
Next 8 data read cycles will read
stored labels. One time only sequence
on each transiton of CR1 to a 1.
Receiver is disabled
Receiver is enabled
RXRDY goes high normally
Blocks RXRDY for one ARINC word
Self test disabled
Self test enabled
No parity errors enabled and 32nd
bit is data
Parity error flag enabled
32 bit "extended mode" enabled and
parity enabled.
8 bit "one byte at a time" mode and
parity enabled.
Label recognition not programmable
Label recognition disabled
Label recognition enabled
OPERATION
HOLT INTEGRATED CIRCUITS
Affecting the
after
HI-6010
a
4-5
These pins must be 5 volt logic levels. There must be a
translator between the
Typically a receiver chip, such as the HI-8482 or HI-8588
is inserted between the ARINC bus and the logic chips.
RXD0 is looking for a high level for zero inputs and RXD1 is
looking for a high level for one inputs. When both inputs are
low this is referred to as the Null state.
SOFTWARE CONTROL OF THE RECEIVER
By writing to the Control Register and reading the Status
Register the controlling processor can operate the receiver
without hardware interrupts.
combination with the wiring of pin 5 was explained above.
The Status Register bits pertaining to the receiver are
explained below:
COMMUNICATING WITH THE CONTROL AND
STATUS REGISTERS
Pin 27, C/ , must be high to read the status register or write
the control register.
errors. There is no provision to read the control register.
LABEL RECOGNITION OPTION
Pin 5 must be high if label recognition is selected in either the
8 or 32 bit modes and all eight label buffers must be written
using redundant labels, if necessary.
The chip compares the incoming label to the stored labels. If
a match is found, the data is processed. If a match is not
found, no indicators of receiving ARINC data are presented.
LOADING LABELS
After the write that changes CR7 from 0 to 1, the next 8 writes
of data (C/ is a zero for data) will load the label registers.
Labels must be loaded whenever pin 5 goes from low to
high.
READING LABELS
After the write that changes CR1 from 0 to 1, the next 8 data
reads are labels.
STATUS BIT VALUE
SR1
SR3
SR4
SR5
SR6
D
PIN 14 - RXD0 and PIN 16 - RXD1
D
0
1
0
1
0
1
0
1
0
1
No receiver data
Receiver data ready
No parity error
Parity error - Parity was even
Receiver data not overwritten
Receiver data was overwritten
Receiver data received without framing error
Framing error - Did not receive exactly 32
good bits
Did not receive first byte
Received first byte - Same flag as pin 13
Reading the status register resets
ARINC bus and these inputs.
MEANING
The Control Register in