HI-6010C HOLTIC [Holt Integrated Circuits], HI-6010C Datasheet - Page 2

• Manufacturer Part Number: HI-6010C
• Description: ARINC 429 TRANSMITTER/RECEIVER FOR 8 BIT BUS
• Manufacturer: HOLTIC [Holt Integrated Circuits]

The receiver logic is independent of the transmitter except in
the following ways:
In self test, the transmitter outputs route to the receiver inputs
internally ignoring the external inputs. Also in self test, the
external receiver clock is replaced with the transmitter clock.
The parity option affects both the receiver and transmitter.
Either both are operational or neither.
HARDWARE CONTROL OF THE RECEIVER
WEF is an error indicator. It goes high for a transmitter
"underwrite" (failure to keep up with byte loading) and pin 2
PIN
10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
11
1
2
3
4
5
6
7
8
9
SYMBOL
RXRDY
TXRDY
RXD0
RXD1
TXD0
TXD1
WEF
RXC
CTS
TXC
HFS
TXE
FCR
V
V
C/
MR
WE
CS
RE
D0
D1
D2
D3
D4
D5
D6
D7
SS
DD
D
1. Self Test
2. Parity Option
PIN 2 - WEF
FUNCTION
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
POWER
POWER
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
I / O
I / O
I / O
I / O
I / O
I / O
I / O
I / O
0.0 Volts
Error indication if high. Status register must be read to determine specific error.
Enables data transmission when low.
Source clock for data transmission. 4 times bit rate.
Hardware feature select.
Master reset, active high.
Low when transmission in progress.
High when data of received word is available.
High when data of a transmitted word may be input.
"Zeroes" data output of transmitter.
"Ones" data output of transmitter.
Source clock for data reception. 4 times bit rate.
First character received flag.
"Zeroes" data input to receiver.
5 Volts ±5%
"Ones" data input to receiver.
Data bus
Data bus
Data bus
Data bus
Data bus
Data bus
Data bus
Data bus
8 bit data bus input control active low.
Chip select, active low.
High for control or status register operations, low for data
8 bit data bus output control, active low.
HOLT INTEGRATED CIRCUITS
HI-6010
4-4
goes high for any one of three receiver errors. The status
register will show which of the three errors occurred:
The possible Receiver sequence errors are:
There are no errors flagged for labels received that don't
match stored labels when in the label recognition mode.
Errors are cleared by MR or by reading the Status Register.
This pin, along with the control register, sets up the
functioning (e.g. modes) of the chip.
Status Register Bit
DESCRIPTION
PIN 5 - HFS and the CONTROL REGISTER
1. RXD0 and RXD1 simultaneously a one.
2. Less than 32 bits before 3 nulls.
3. More than 32 bits.
SR3
SR4
SR5
Received a parity error
Data Overwritten
Receiving sequence error
Error
If HFS is low, the