ISL6610 INTERSIL [Intersil Corporation], ISL6610 Datasheet - Page 7

• Manufacturer Part Number: ISL6610
• Description: Dual Synchronous Rectified MOSFET Drivers
• Manufacturer: INTERSIL [Intersil Corporation]

the bootstrap capacitor when exposed to excessively large
negative voltage swing at the PHASE node. Typically, such
large negative excursions occur in high current applications
that use D
parasitic inductance. The following equation helps select a
proper bootstrap capacitor size:
where Q
at V
control MOSFETs. The ΔV
allowable droop in the rail of the upper gate drive.
As an example, suppose two HAT2168 FETs are chosen as
the upper MOSFETs. The gate charge, Q
sheet is 12nC at 5V (V
Q
will assume a 100mV droop in drive voltage over the PWM
cycle. We find that a bootstrap capacitance of at least
0.264μF is required. The next larger standard value
capacitance is 0.33µF. A good quality ceramic capacitor is
recommended.
Power Dissipation
Package power dissipation is mainly a function of the
switching frequency (F
external gate resistance, and the selected MOSFET’s
internal gate resistance and total gate charge. Calculating
the power dissipation in the driver for a desired application is
critical to ensure safe operation. Exceeding the maximum
allowable power dissipation level will push the IC beyond the
maximum recommended operating junction temperature of
+125°C. The maximum allowable IC power dissipation for
C
Q
GATE
BOOT_CAP
GATE
FIGURE 2. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
GS1
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
=
is calculated to be 26.4nC at 5.5V PVCC level. We
0.0
G1
gate-source voltage and N
Q
----------------------------------- - N
20nC
2
-PAK and D-PAK MOSFETs or excessive layout
G1
is the amount of gate charge per upper MOSFET
≥
V
0.1
VOLTAGE
------------------------------------- -
ΔV
•
GS1
PVCC
BOOT_CAP
Q
0.2
GATE
50nC
Q
GATE
•
GS
SW
0.3
Q1
) gate-source voltage. Then the
), the output drive impedance, the
BOOT_CAP
= 100nC
ΔV
0.4
BOOT
7
0.5
(V)
Q1
0.6
term is defined as the
is the number of
G
, from the data
0.7
0.8
ISL6610, ISL6610A
0.9
(EQ. 1)
1.0
the SO14 package is approximately 1W at room
temperature, while the power dissipation capacity in the
QFN packages, with an exposed heat escape pad, is around
2W. See Layout Considerations paragraph for thermal
transfer improvement suggestions. When designing the
driver into an application, it is recommended that the
following calculation is used to ensure safe operation at the
desired frequency for the selected MOSFETs. The total gate
drive power losses due to the gate charge of MOSFETs and
the driver’s internal circuitry and their corresponding average
driver current can be estimated with Equations 2 and 3,
respectively,
where the gate charge (Q
particular gate to source voltage (V
corresponding MOSFET datasheet; I
quiescent current with no load at both drive outputs and can
be negligible; N
MOSFETs, respectively. The factor 2 is the number of active
channels. The I
driver without capacitive load and is typically negligible.
The total gate drive power losses are dissipated among the
resistive components along the transition path. The drive
resistance dissipates a portion of the total gate drive power
losses, the rest will be dissipated by the external gate
resistors (R
interfering with the operation shoot-through protection
circuitry) and the internal gate resistors (R
MOSFETs. Figures 3 and 4 show the typical upper and lower
gate drives turn-on transition path. The power dissipation on
the driver can be roughly estimated as:
P
P
P
R
I
P
DR
DR
DR_UP
DR_LOW
EXT2
Qg_TOT
P
P
=
=
Qg_Q2
Qg_Q1
2
2
=
•
=
•
R
⎛
⎜
⎝
=
=
(
Q
----------------------------- -
⎛
⎜
⎝
G1
G1
P
--------------------------------------
R
=
⎛
⎜
⎝
2
G1
=
DR_UP
V
HI1
--------------------------------------
R
+
•
and R
Q
-------------------------------------- - F
Q
-------------------------------------- - F
GS1
HI2
Q
Q1
(
•
R
-------------
R
N
G2
P
G1
+
N
V
GI1
HI1
R
Q1
Qg_Q1
Q1
and N
R
+
V
V
CC
HI2
•
•
+
GS2
EXT1
R
GS1
G2
PVCC
PVCC
P
+
EXT2
product is the quiescent power of the
DR_LOW
Q
----------------------------- -
, should be a short to avoid
+
Q2
G2
G1
+
V
P
2
2
GS2
+
--------------------------------------- -
R
Qg_Q2
are number of upper and lower
•
•
•
and Q
LO1
--------------------------------------- -
R
R
N
LO2
)
EXT2
Q2
SW
SW
R
+
+
LO1
R
I
⎞
⎟
⎠
)
Q
R
+
+
LO2
•
G2
GS1
•
•
•
EXT1
N
R
I
F
N
Q
=
Q
VCC
Q2
SW
) is defined at a
EXT2
Q1
R
•
and V
is the driver’s total
G2
VCC
⎞
⎟
⎠
+
GI1
•
⎞
⎟
⎠
I
+
Q
P
---------------------
•
GS2
R
-------------
N
Qg_Q1
P
---------------------
and R
GI2
November 22, 2006
Qg_Q2
Q2
2
2
) in the
GI2
(EQ. 3)
FN6395.0
(EQ. 2)
(EQ. 4)
) of