PSD913G2 STMICROELECTRONICS [STMicroelectronics], PSD913G2 Datasheet - Page 53

• Manufacturer Part Number: PSD913G2
• Description: Configurable Memory System on a Chip for 8-Bit Microcontrollers
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

The
PSD935G2
Functional
Blocks
(cont.)
52
PSD9XX Family
9.4.5 Ports A, B and C – Functionality and Structure
Ports A and B have similar functionality and structure, as shown in Figure 21. The two
ports can be configured to perform one or more of the following functions:
Figure 21 Port A, B and C
MCU I/O Mode
GPLD Output – Combinatorial PLD outputs.
PLD Input
Address In – Additional high address inputs may be latched by ALE.
Open Drain/Slew Rate – pins PC[7:0]can be configured to fast slew rate,
WR
WR
– Input to the PLDs.
GPLD OUTPUT
READ MUX
DATA OUT
DIR REG.
D
D
REG.
P
D
B
Q
Q
pins PA[7:0] and PB[7:0] can be configured to Open Drain
Mode.
PLD INPUT
DATA IN
DATA OUT
OUTPUT
OUTPUT
SELECT
MUX
PSD935G2
PORT PIN