PPC440GR-3PBFFFCX AMCC [Applied Micro Circuits Corporation], PPC440GR-3PBFFFCX Datasheet - Page 75

• Manufacturer Part Number: PPC440GR-3PBFFFCX
• Description: Power PC 440GR Embedded Processor
• Manufacturer: AMCC [Applied Micro Circuits Corporation]

Figure 10. DDR SDRAM Read Data Path
Table 23. I/O Timing—DDR SDRAM T
Notes:
1. T
2. T
3. Clock speed for the values in the table is 133MHz.
4. The time values for T
In the following examples, the data strobes (DQS) and the data are shown to be coincident. There is actually a
slight skew as specified by the SDRAM specifications, and there can be additional skew due to loading and signal
routing. It is recommended that the signal length for all of the eight DQS signals be matched.
AMCC Proprietary
440GR – PPC440GR Embedded Processor
SIN
DIN
Signal Name
DQS
Data
= Delay from DQS at package pin to C on Stage 1 FF.
= Delay from data at package pin to D on Stage 1 FF.
DQS0
DQS1
DQS2
DQS3
DQS8
Package pins
PLB Clock
Cycle
Delay
1/4
D
Stage 1
SIN
FF,
XL
C
minimum
T
include 1/4 of a cycle at 133MHz (7.5ns x 0.25 = 1.875 ns).
SIN
2.74
2.75
2.74
2.76
2.77
Q
Programmed
Read Clock
FF Timing:
(ns)
T
T
T
Delay
IS
IH
P
= Propagation delay (D to Q or C to Q) = 0.4ns maximum
= Input setup time = 0.2ns
= Input hold time = 0.1ns
D
Stage 2
SIN
FF
maximum
C
T
and T
SIN
3.70
3.69
3.69
3.69
3.68
Q
(ns)
DIN
MemData00:07
MemData08:15
MemData16:23
MemData24:31
ECC0:7
D
Stage 3
FF
Signal Name
C
Q
(SDRAM0_TR1)
Read Select
Mux
Preliminary Data Sheet
minimum
T
ECC
DIN
0.86
0.87
0.89
0.88
0.89
Revision 1.16 – July 19, 2006
(ns)
FF: Flip-Flop
XL: Transparent Latch
D
RDSP
FF
C
Q
maximum
T
DIN
1.87
1.86
1.86
1.85
1.83
(ns)
PLB bus
75