PPC440GR-3PBFFFCX AMCC [Applied Micro Circuits Corporation], PPC440GR-3PBFFFCX Datasheet
PPC440GR-3PBFFFCX
Related parts for PPC440GR-3PBFFFCX
PPC440GR-3PBFFFCX Summary of contents
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... Programmable General Purpose Timers (GPT). Description Designed specifically to address high-end embedded applications, the PowerPC 440GR (PPC440GR) provides a high-performance, low- power solution that interfaces to a wide range of peripherals and incorporates on-chip power management features. This chip contains a high-performance RISC ...
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... General Purpose IO (GPIO) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Universal Interrupt Controller (UIC JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Signal Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Device Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Spread Spectrum Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 DDR SDRAM I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 DDR SDRAM Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 DDR SDRAM Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Strapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Serial EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 2 440GR – PPC440GR Embedded Processor AMCC Proprietary ...
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... PPC440GR Embedded Processor Figures Figure 1. Order Part Number Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. PPC440GR Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 3. 35mm, 456-Ball E-PBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 4. Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Figure 5. Input Setup and Hold Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Figure 6. Output Delay and Float Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Figure 7. DDR SDRAM Simulation Signal Termination Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Figure 8 ...
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... For information on the availability of the following parts, contact your local AMCC sales office. Order Part Number Product Name (see Notes:) PPC440GR PPC440GR-3pbfffCx PPC440GR PPC440GR-3pbfffCx Notes Module Package type B = E-PBGA and contains lead E-PBGA and is lead-free (RoHS compliant Chip revision level A = Revision level A (1. Revision level B (1 ...
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... D-Cache Performance Monitor PLB4 (128 bits) Controller DDR SDRAM Controller 266MHz max - 13-bit addr - 32-bit data The PPC440GR is a system on a chip (SOC) using IBM CoreConnect Bus AMCC Proprietary Power Mgmt DCRs GPIO DCR Bus Trace On-chip Peripheral Bus (OPB) 32KB ...
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... Preliminary Data Sheet Address Maps The PPC440GR incorporates two address maps. The first is a fixed processor System Memory Address Map. This address map defines the possible contents of various address regions which the processor can access. The second is the DCR Address Map for Device Configuration Registers (DCRs). The DCRs are accessed by software running on the PPC440GR processor through the use of Table 1 ...
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... PPC440GR Embedded Processor Table 1. System Memory Address Map (Sheet Function Reserved General Purpose Timer Reserved UART0 Reserved UART1 Reserved UART2 Reserved UART3 Reserved IIC0 Reserved IIC1 Internal Peripherals Reserved SPI Reserved OPB Arbiter Reserved GPIO0 Controller Reserved GPIO1 Controller ...
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... DMA to PLB 128 Controller Reserved Notes: 1. DCR address space is addressable with bits (1024 or 1K unique addresses). Each unique address represents a single 32-bit (word) register. One kiloword (1024W) equals 4KB (4096 B). 8 440GR – PPC440GR Embedded Processor Start Address End Address 000 3FF 000 ...
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... PPC440GR Embedded Processor PowerPC 440 Processor Core The PowerPC 440 processor core is designed for high-end applications: RAID controllers, SAN, iSCSI, routers, switches, printers, set-top boxes, etc. It implements the Book E PowerPC embedded architecture and uses the 128-bit version of IBM’s on-chip CoreConnect Bus Architecture. ...
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... PLB 128), maximum 1.1GB/s (no simultaneous read and write) • OPB – 32-bit data path – 32-bit address – 66.66MHz • DCR – 32-bit data path – 10-bit address 10 440GR – PPC440GR Embedded Processor AMCC Proprietary ...
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... PPC440GR Embedded Processor PCI Interface The PCI interface allows connection of PCI devices to the PowerPC processor and local memory. This interface is designed to Version 2.2 of the PCI Specification and supports 32- bit PCI devices. Reference Specifications: • PowerPC CoreConnect Bus (PLB) Specification Version 3.1 • ...
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... External master can control EBC slaves for own access and control Ethernet Controller Interface Ethernet support provided by the PPC440GR interfaces to the physical layer but the PHY is not included on the chip: • One to two 10/100 interfaces running in full- and half-duplex modes – ...
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... PPC440GR Embedded Processor DMA to PLB 128 Controller This DMA controller provides a DMA interface dedicated to the 128-bit PLB. Features include: • Support for memory-to-memory, peripheral-to-memory, and memory-to-peripheral transfers • Scatter/gather capability • 128-byte buffer with programmable thresholds ...
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... GPIOs are multiplexed with other functions. DCRs control whether a particular pin that has GPIO capabilities acts as a GPIO or is used for another purpose. • Each GPIO output is separately programmable to emulate an open drain driver (that is, drives to zero, tri-stated if output bit is 1). 14 440GR – PPC440GR Embedded Processor AMCC Proprietary ...
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... PPC440GR Embedded Processor Universal Interrupt Controller (UIC) Two Universal Interrupt Controllers (UIC) are employed. They provide control, status, and communications necessary between the external and internal sources of interrupts and the on-chip PowerPC processor. Processor specific interrupts (for example, page faults) do not use UIC resources. ...
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... 440GR – PPC440GR Embedded Processor ® PPC440GR 30 TYP 1YWWBZZZZZ PPC440GR-nprffft 1. All dimensions are in mm. 2. Package is available in both lead-free (RoHS compliant) and leaded versions. A 35.0 31.75 Thermal Balls ...
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... PPC440GR Embedded Processor Signal Lists The following table lists all the external signals in alphabetical order and shows the ball (pin) number on which the signal appears. Multiplexed signals are shown with the default signal (following reset) not in brackets and alternate signals in brackets. Multiplexed signals appear alphabetically multiple times in the list— ...
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... EMCTxD1, EMC0TxD1, EMC1TxD[GPIO17] EMCTxD2, EMC1TxD0[GPIO18][NFCLE] EMCTxD3, EMC1TxD1[GPIO19][NFALE] EMCTxEn, EMC0TxEn, EMCSync[GPIO24] EMCTxErr, EMC1TxEn[GPIO23][NFWEn] [EOT0/TC0]IRQ9[GPIO48] [EOT1/TC1]IRQ6[GPIO45] [EOT2/TC2]PerAddr05[GPIO02] [EOT3/TC3]PerAddr02[GPIO05] ExtAck[GPIO30] ExtReq[GPIO27] ExtReset 18 440GR – PPC440GR Embedded Processor Ball Interface Group P02 N02 M01 M02 DDR SDRAM N03 N04 L02 M03 AC16 ...
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... PPC440GR Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 3 of 24) Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND ...
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... GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 20 440GR – PPC440GR Embedded Processor Ball Interface Group M15 M25 N05 N11 N13 N14 N15 N16 P11 P12 P13 P14 P16 P22 R12 R14 ...
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... PPC440GR Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 5 of 24) Signal Name GND GND GND GND GND GND GND GND GND GND GND GND AMCC Proprietary Revision 1.16 – July 19, 2006 Preliminary Data Sheet Ball Interface Group AD03 AD24 AE01 AE02 ...
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... EMC1TxD1[NFALE] [GPIO20]EMCRxErr, EMC0RxErr [GPIO21]EMCDV, EMC1CrsDV[NFREn] [GPIO22]EMCCrS, EMC0CrsDV [GPIO23]EMCTxErr, EMC1TxEn[NFWEn] [GPIO24]EMCTxEn, EMC0TxEn, EMCSync [GPIO25]EMCCD, EMC1RxErr[NFRdyBusy] GPIO26 [GPIO27]ExtReq GPIO28 [GPIO29]HoldAck [GPIO30]ExtAck [GPIO31]BusReq 22 440GR – PPC440GR Embedded Processor Ball Interface Group C08 B06 A05 D08 C07 B04 C06 A04 B07 B10 A10 E04 ...
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... PPC440GR Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 7 of 24) Signal Name GPIO32 GPIO33 [GPIO34]UART0_DCD/UART1_CTS/UART2_Tx [GPIO35]UART0_DSR/UART1_RTS/UART2_Rx [GPIO36]UART0_CTS/UART3_Rx [GPIO37]UART0_RTS/UART3_Tx [GPIO38]UART0_DTR/UART1_Tx [GPIO39]UART0_RI/UART1_Rx [GPIO40]IRQ0 [GPIO41]IRQ1 [GPIO42]IRQ2 [GPIO43]IRQ3 [GPIO44]IRQ4[DMAAck1] [GPIO45]IRQ6[EOT1/TC1] [GPIO46]IRQ7[DMAReq0] [GPIO47]IRQ8[DMAAck0] [GPIO48]IRQ9[EOT0/TC0] [GPIO49]TrcBS0 [GPIO50]TrcBS1 [GPIO51]TrcBS2 [GPIO52]TrcES0 [GPIO53]TrcES1 [GPIO54]TrcES2 [GPIO55]TrcES3 [GPIO56]TrcES4 [GPIO57]TrcTS0 [GPIO58]TrcTS1 [GPIO59]TrcTS2 ...
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... IRQ9[GPIO48][EOT0/TC0] [LeakTest]HoldPri MemAddr00 MemAddr01 MemAddr02 MemAddr03 MemAddr04 MemAddr05 MemAddr06 MemAddr07 MemAddr08 MemAddr09 MemAddr10 MemAddr11 MemAddr12 MemClkOut0 MemClkOut0 24 440GR – PPC440GR Embedded Processor Ball Interface Group U24 IIC1 Peripheral V25 D03 G04 F02 G02 G25 Interrupts AC12 H23 B24 D18 A19 V24 ...
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... PPC440GR Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 9 of 24) Signal Name MemData00 MemData01 MemData02 MemData03 MemData04 MemData05 MemData06 MemData07 MemData08 MemData09 MemData10 MemData11 MemData12 MemData13 MemData14 MemData15 MemData16 MemData17 MemData18 MemData19 MemData20 MemData21 MemData22 MemData23 MemData24 MemData25 MemData26 MemData27 ...
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... No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball 26 440GR – PPC440GR Embedded Processor Ball Interface Group AC14 D06 C06 A04 B07 NAND Flash AF14 AC16 AF17 AF18 F06 F07 F08 F09 F10 ...
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... PPC440GR Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 11 of 24) Signal Name No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball ...
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... No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball 28 440GR – PPC440GR Embedded Processor Ball Interface Group J20 J21 K06 K07 K08 K09 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 ...
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... PPC440GR Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 13 of 24) Signal Name No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball ...
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... No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball 30 440GR – PPC440GR Embedded Processor Ball Interface Group T09 T10 T17 T18 T19 T20 T21 U06 U07 U08 U09 U10 U11 U12 U13 U14 ...
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... PPC440GR Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 15 of 24) Signal Name No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball ...
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... 440GR – PPC440GR Embedded Processor Ball Interface Group AA06 AA07 AA08 AA09 AA10 AA11 AA12 AA13 A physical ball does not exist at these ball coordinates. AA14 AA15 AA16 AA17 AA18 AA19 AA20 ...
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... PPC440GR Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 17 of 24) Signal Name PCIAD00 PCIAD01 PCIAD02 PCIAD03 PCIAD04 PCIAD05 PCIAD06 PCIAD07 PCIAD08 PCIAD09 PCIAD10 PCIAD11 PCIAD12 PCIAD13 PCIAD14 PCIAD15 PCIAD16 PCIAD17 PCIAD18 PCIAD19 PCIAD20 PCIAD21 PCIAD22 PCIAD23 PCIAD24 PCIAD25 PCIAD26 PCIAD27 ...
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... PCIGnt4 PCIGnt5 PCIIDSel PCIINT PCIIRDY PCIPar PCIPErr PCIReq0/Gnt PCIReq1 PCIReq2 PCIReq3 PCIReq4 PCIReq5 PCIReset PCISErr PCIStop PCITRDY 34 440GR – PPC440GR Embedded Processor Ball Interface Group D17 L24 A25 PCI D25 H25 E24 G26 PCI D20 PCI E25 PCI C23 PCI D24 ...
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... PPC440GR Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 19 of 24) Signal Name PerAddr02[GPIO05][EOT3/TC3] PerAddr03[GPIO04][DMAAck3] PerAddr04[GPIO03][DMAReq3] PerAddr05[GPIO02][EOT2/TC2] PerAddr06[GPIO01][DMAAck2] PerAddr07[GPIO00][DMAReq2] PerAddr08 PerAddr09 PerAddr10 PerAddr11 PerAddr12 PerAddr13 PerAddr14 PerAddr15 PerAddr16 PerAddr17 PerAddr18 PerAddr19 PerAddr20 PerAddr21 PerAddr22 PerAddr23 ...
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... PerData11 PerData12 PerData13 PerData14 PerData15 PerErr[GPIO11] PerOE PerReady PerR/W PerWBE0 PerWBE1 PSROOut RAS [RcvrInh]HoldReq RefEn RejectPkt[DrvrInh1] 36 440GR – PPC440GR Embedded Processor Ball Interface Group H01 K04 G01 J03 J04 H03 E01 G03 External Slave Peripheral H04 E02 D01 F03 C01 F04 ...
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... PPC440GR Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 21 of 24) Signal Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved SAGND SAV DD SCPClkOut[IIC1SClk] SCPDI[IIC1SData] SCPDO AMCC Proprietary Revision 1.16 – ...
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... SV REF2A SV REF2B SysClk SysErr SysReset TCK TDI TDO TestEn TmrClk1 TmrClk2 TMS TrcBS0[GPIO49] TrcBS1[GPIO50] TrcBS2[GPIO51] TrcClk 38 440GR – PPC440GR Embedded Processor Ball Interface Group P05 R11 R16 T12 T15 W05 W22 Y05 Y22 Power AA05 AA22 AB06 AB07 AB08 AB14 AB19 ...
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... PPC440GR Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 23 of 24) Signal Name TrcES0[GPIO52] TrcES1[GPIO53] TrcES2[GPIO54] TrcES3[GPIO55] TrcES4[GPIO56] TrcTS0[GPIO57] TrcTS1[GPIO58] TrcTS2[GPIO59] TrcTS3[GPIO60] TrcTS4[GPIO61] TrcTS5[GPIO62] TrcTS6[GPIO63] TRST UART0_CTS/UART3_Rx[GPIO36] UART0_RTS/UART3_Tx[GPIO37] UART0_Rx UART0_Tx UART0_DCD/UART1_CTS/UART2_Tx[GPIO34] UART0_DSR/UART1_RTS/UART2_Rx[GPIO35] UART0_DTR/UART1_Tx[GPIO38] UART0_RI/UART1_Rx[GPIO39] UARTSerClk AMCC Proprietary Revision 1.16 – July 19, 2006 ...
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... 440GR – PPC440GR Embedded Processor Ball Interface Group E05 E10 E11 E12 E15 E16 E17 E22 K05 K22 L05 L22 M05 M22 M14 N12 Power P15 R05 R13 R22 ...
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... PPC440GR Embedded Processor In the following table, only the primary (default) signal name is shown for each pin. Multiplexed or multifunction signals are marked with an asterisk (*). To determine what signals or functions are multiplexed on those pins, look up the primary signal name in Table 3, Signals Listed Alphabetically. ...
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... E21 F21 DD V E22 F22 DD E23 PCIStop F23 E24 PCIGnt5 F24 E25 PCIIRDY F25 E26 PCIC3/BE3 F26 42 440GR – PPC440GR Embedded Processor Signal Name Ball Signal Name GND G01 PerData02 IRQ2* G02 IRQ3* PerData11 G03 PerData07 PerData13 G04 IRQ1 G05 DD ...
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... PPC440GR Embedded Processor Table 4. Signals Listed by Ball Assignment (Sheet Ball Signal Name Ball J01 DM2 K01 J02 CAS K02 J03 PerData03 K03 J04 PerData04 K04 J05 GND K05 J06 No ball K06 J07 No ball K07 J08 No ball K08 J09 ...
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... N21 No ball P21 OV N22 P22 DD N23 PCIAD28 P23 N24 UART0_DTR* P24 N25 PCIReq0/Gnt P25 N26 PCIAD29 P26 44 440GR – PPC440GR Embedded Processor Signal Name Ball Signal Name MemAddr00 R01 BankSel2 ECC0 R02 BankSel1 SV R03 MemAddr10 REF2A MemAddr01 R04 BankSel0 SV V R05 ...
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... PPC440GR Embedded Processor Table 4. Signals Listed by Ball Assignment (Sheet Ball Signal Name Ball U01 MemAddr04 V01 U02 MemData31 V02 U03 MemData29 V03 U04 MemAddr06 V04 V U05 V05 DD U06 No ball V06 U07 No ball V07 U08 No ball V08 U09 No ball ...
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... AA21 No ball AB21 SV AA22 AB22 DD AA23 BusReq* AB23 AA24 TrcBS2* AB24 AA25 ExtAck* AB25 AA26 GND AB26 46 440GR – PPC440GR Embedded Processor Signal Name Ball Signal Name SysErr AC01 GND MemAddr09 AC02 MemData20 TrcES2* AC03 MemData19 TrcES3* AC04 GND V AC05 MemData17 DD ...
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... PPC440GR Embedded Processor Table 4. Signals Listed by Ball Assignment (Sheet Ball Signal Name Ball AE01 GND AF01 AE02 GND AF02 AE03 MemData16 AF03 AE04 MemSelfRef AF04 AE05 DM0 AF05 SV AE06 AF06 REF2B AE07 MemData13 AF07 AE08 MemData11 AF08 AE09 ...
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... PPC440GR has control of the external bus. When during the course of normal chip operation an external master gains ownership of the external bus, these same pins are used as inputs which are driven by the external master and received by the EBC in the PPC440GR. In this example, the pins are also bidirectional, serving both as inputs and outputs. ...
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... PPC440GR Embedded Processor Multimode Signals In some cases (for example, Ethernet) the function of a pin may vary with different modes of operation. When a pin has multiple signal names assigned to distinguish different modes of operation, all of the names are shown. Strapping Pins One group of pins is used as strapped inputs during system reset. These pins function as strapped inputs only during reset and are used for other functions during normal operation (see “ ...
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... Reports address parity errors, data parity errors on the Special PCISErr Cycle command, or other catastrophic system errors. Indicates the current target is requesting the master to stop the PCIStop current transaction. I ndicates the target agent’s ability to complete the current data PCITRDY phase of the transaction. 50 440GR – PPC440GR Embedded Processor Description I/O I/O . I/O I I/O I ...
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... PPC440GR Embedded Processor Table 7. Signal Functional Description (Sheet Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3kΩ to 3.3V) 3. Must pull down (recommended value is 1kΩ not used, must pull up (recommended value is 3kΩ to 3.3V not used, must pull down (recommended value is 1kΩ) 6. Strapping input during reset ...
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... MII: Transmit data. EMC1TxD0:1 RMII B: Transmit data. EMCTxEn, MII: Transmit data enabled. EMC0TxEn, RMII A: Transmit data enabled. EMCSync SMII: Sync signal. EMCTxErr, MII: Transmit error. EMC1TxEn RMII B: Transmit data enabled. RejectPkt External request to reject a packet. 52 440GR – PPC440GR Embedded Processor Description I/O I/O I/O I/O O I/O I/O I/O I/O I/O I I/O I/O O ...
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... Note: PerData00 is the most significant bit (msb) on this bus. Used by either peripheral controller or DMA controller depending upon the type of transfer involved. When the PerOE PPC440GR is the bus master, it enables the selected device to drive the bus. Used by a peripheral slave to indicate it is ready to transfer PerReady data ...
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... If not used, must pull down (recommended value is 1kΩ) 6. Strapping input during reset; pull-up or pull-down required Signal Name External Master Peripheral Interface Bus Request. Used when the PPC440GR needs to regain BusReq control of peripheral interface from an external master. External Acknowledgement. Used by the PPC440GR to ExtAck indicate that a data transfer occurred ...
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... PPC440GR Embedded Processor Table 7. Signal Functional Description (Sheet Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3kΩ to 3.3V) 3. Must pull down (recommended value is 1kΩ not used, must pull up (recommended value is 3kΩ to 3.3V not used, must pull down (recommended value is 1kΩ) 6. Strapping input during reset ...
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... Receiver Inhibit. Active only when TestEn is active. ModeCtrl Mode Control. LeakTest Leakage Test. RefEn Reference Enable. Driver Inhibit. Used for test purposes only. Tie up as specified DrvrInh1:2 in Note 2 for normal operation. PSROOut Module characterization and screening. 56 440GR – PPC440GR Embedded Processor Description I/O Clock ...
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... PPC440GR Embedded Processor Table 7. Signal Functional Description (Sheet Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3kΩ to 3.3V) 3. Must pull down (recommended value is 1kΩ not used, must pull up (recommended value is 3kΩ to 3.3V not used, must pull down (recommended value is 1kΩ) 6. Strapping input during reset ...
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... during each power up or power down event. 2. The analog voltages used for the on-chip PLLs can be derived from the logic voltage, but must be filtered before entering the PPC440GR. A separate filter, as shown below, is recommended for each voltage This value is not a specification of the operational temperature range stress rating only. ...
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... PPC440GR Embedded Processor Table 9. Recommended DC Operating Conditions (Sheet Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended conditions can affect device reliability. Parameter Logic Supply Voltage I/O Supply Voltage SDRAM Supply Voltage PLL Supply Voltages ...
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... DD 3. The analog voltages used for the on-chip PLLs can be derived from the logic voltage, but must be filtered before entering the PPC440GR. See “Absolute Maximum Ratings” on page 58. Power Sequencing Startup sequencing of the power supply voltages is not required. However, a power-down cycle must complete ...
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... PPC440GR Embedded Processor Table 12. V Supply Power Dissipation DD Frequency (MHz) 333 400 533 667 Notes: 1. Power is based on V specified in the table and T DD that exercises each core with representative traffic. Table 13. DC Power Supply Loads Parameter V (1.5V) active operating current ...
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... The following heat sinks were used in the above thermal analysis: ALPHA W35-15W (35mm x 35mm x15mm) ALPHA LPD35-15B (35mm x 35mm x15mm) The heat sinks are manufactured by: Alpha Novatech, Inc. (www.alphanovatech.com) 473 Sapena Court, #12 Santa Clara, CA 95054 Phone: 408-567-8082 62 440GR – PPC440GR Embedded Processor Symbol Package 0 (0) E-PBGA 20.0 θ JA TE-PBGA 15 ...
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... PPC440GR Embedded Processor Table 15. Clocking Specifications Symbol Parameter SysClk Input F Frequency C T Period C T Edge stability (cycle-to-cycle jitter High time CH T Low time CL ≥ Note: Input slew rate 1V/ns MemClkOut and PLB Clock F Frequency C T Period C T High time ...
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... The 1.5% tolerance assumes that the connected device is running at precise baud rates. 2. Ethernet operation is unaffected. 3. IIC operation is unaffected the system designer to ensure that any SSCG used with the PPC440GR meets the above Important: requirements and does not adversely affect other aspects of the system. 64 440GR – ...
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... PPC440GR Embedded Processor I/O Specifications Table 16. Peripheral Interface Clock Timings Parameter PCIClk input frequency (asynchronous mode) PCIClk period (asynchronous mode) PCIClk input high time PCIClk input low time EMCMDClk output frequency EMCMDClk period EMCMDClk output high time EMCMDClk output low time ...
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... Preliminary Data Sheet Figure 5. Input Setup and Hold Waveform Clock Inputs Figure 6. Output Delay and Float Timing Waveform Clock T max OV T min Outputs OH High (Drive) Float (High-Z) Low (Drive) 66 440GR – PPC440GR Embedded Processor T min T min IS IH Valid T max OV T min OH Valid T max ...
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... PPC440GR Embedded Processor Table 17. I/O Specifications—All Speeds (Sheet Notes: 1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. Input (ns) Signal Setup Time Hold Time (T min PCI Interface PCIAD31:00 5 PCIC3:0/BE3:0 5 PCIClk dc PCIDevSel 5 PCIFrame 5 PCIGnt0:5 n/a PCIIDSel 5 PCIINT n/a PCIIRDY ...
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... TDI n/a TDO n/a TMS n/a TRST n/a System Interface SysClk n/a TmrClk1:2 n/a SysReset n/a Halt n/a SysErr n/a TestEn n/a DrvrInh1:2 n/a RcvrInh n/a GPIO00:63 n/a PSROOut n/a Trace Interface TrcClk n/a TrcBS0:2 n/a TrcES0:4 n/a TrcTS0:6 n/a 68 440GR – PPC440GR Embedded Processor Output (ns) Valid Delay Hold Time min) (T max) (T min n n n/a n/a n n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a ...
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... PPC440GR Embedded Processor Table 18. I/O Specifications—333MHz to 533MHz Notes: 1. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 1.3ns. Input (ns) Signal Setup Time Hold Time (T min External Slave Peripheral Interface DMAAck0:1 n/a DMAAck2:3 n/a DMAReq0:3 11.7 EOT0:1/TC0:1 11 ...
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... Note: This diagram illustrates the model of the DDR SDRAM interface used when generating simulation timing data not a recommended physical circuit design for this interface. An actual interface design will depend on many factors, including the type of memory used and the board layout. 70 440GR – PPC440GR Embedded Processor 10pF 120Ω 10pF ...
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... PPC440GR Embedded Processor Table 19. DDR SDRAM Output Driver Specifications Signal Path Write Data MemData00:07 MemData08:15 MemData16:23 MemData24:31 ECC0:7 DM0:8 MemClkOut0 MemAddr00:12 BA0:1 RAS CAS WE BankSel0:3 ClkEn0:3 DQS0:8 AMCC Proprietary Revision 1.16 – July 19, 2006 Preliminary Data Sheet Output Current (mA) I/O H (maximum) 15 ...
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... Setup time for data signals (minimum time data is valid before rising/falling edge of DSQ Hold time for data signals (minimum time data is valid after rising/falling edge of DSQ Delay from rising/falling edge of clock to the rising/falling edge of DQS DS 72 440GR – PPC440GR Embedded Processor ...
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... PPC440GR Embedded Processor The timing data in the following tables is based on simulation runs using Einstimer. Note: Table 20. I/O Timing—DDR SDRAM T Notes: 1. All of the DQS signals are referenced to MemClkOut0(0). 2. Clock speed is 133MHz. 3. The T values in the table include 3 cycle at 133MHz (7.5ns x 0.75 = 5.625 ns). ...
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... In operation, following the receipt of an address and read command from the PPC440GR, the SDRAM generates data and the DQS signals coincident with MemClkOut0. The data is latched into the PPC440GR using a DQS signal that is delayed 1 cycle. In order to accommodate timing variations introduced by the system designs using this chip, the three-stage data path shown below is used to eliminate metastability and allow data sampling to be adjusted for minimum latency ...
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... PPC440GR Embedded Processor Figure 10. DDR SDRAM Read Data Path Package pins Stage FF, Data XL C 1/4 Programmed Cycle DQS Read Clock Delay Delay PLB Clock FF Timing Input setup time = 0.2ns Input hold time = 0.1ns Propagation delay ( 0.4ns maximum P Table 23. I/O Timing— ...
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... Except for small, low frequency memory systems with the memory located physically close (1) to the PPC440GR unlikely that Stage 1 data can be sampled. When the data comes later necessary to sample Stage 2 or Stage 3 data. (see Examples 2 and 3). Another way to get the desired data-to-PLB timing to allow Stage 1 sampling is to buffer MemClkOut0 and skew it enough to guarantee the timing ...
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... PPC440GR Embedded Processor Example 2: In this example Read Clock is delayed almost 1/2 cycle. Without ECC, Stage 2 data can be sampled at is enabled, Stage 3 data must be sampled (see Example 3). In this example, T the software. Figure 12. DDR SDRAM Read Cycle Timing—Example 2 DQS at pin ...
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... Data in at RDSP with ECC Low High Data out RDSP with ECC Low T = Propagation delay from Stage 2 input to RDSP input w/o ECC Propagation delay from Stage 2 input to RDSP input with ECC TE 78 440GR – PPC440GR Embedded Processor ...
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... PPC440GR Embedded Processor Initialization The PPC440GR provides the option for setting initial parameters based on default values or by reading them from a slave PROM attached to the IIC0 bus (see “Serial EEPROM” below). Some of the default values can be altered by strapping on external pins (see “Strapping” below). ...
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... PPC440GR Embedded Processor Contents of Modification Initial creation of document. Restore second DMA controller and make PVR and JTAG ID same as 440EP. Update DDR SDRAM timing. Update I/O definitions. Misc. corrections Remove 400MHz and 466MHz part numbers. Remove reference to USB end points. ...
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... PPC440GR Embedded Processor Printed in the United States of America, August 4, 2006 The following are trademarks of AMCC Corporation in the United States, or other countries, or both: AMCC Other company, product, and service names may be trademarks or service marks of others. Preliminary Edition (August 4, 2006) This document contains information on a new product under development by AMCC. ...
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... AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. AMCC is a registered Trademark of Applied Micro Circuits Corporation. Copyright © 2006 Applied Micro Circuits Corporation. 82 440GR – PPC440GR Embedded Processor Applied Micro Circuits Corporation http://www.amcc.com AMCC Proprietary ...