PPC405GP-3BE133C AMCC [Applied Micro Circuits Corporation], PPC405GP-3BE133C Datasheet - Page 56

• Manufacturer Part Number: PPC405GP-3BE133C
• Description: Power PC 405GP Embedded Processor
• Manufacturer: AMCC [Applied Micro Circuits Corporation]

405GP – Power PC 405GP Embedded Processor
56
PPC405GP Strapping Pin Assignments
PCI Divider from PLB
External Bus Divider from PLB
ROM Width
ROM Location
PCI Asynchronous Mode Enable
PCI Arbiter Enable
Note:
1. The tune bits adjust parameters that control PLL jitter. The recommended values minimize jitter for the PLL implemented in the
2. Not all combinations of dividers produce valid operating configurations. Frequencies must be within the limits specified in “Clocking
3. Additional consideration must be given to pins that normally function as Trace signals. Improved design margin can be gained by using
PPC405GP. These bits are shown for information only; and do not require modification except in special clocking circumstances such as
spread spectrum clocking. For details on the use of Spread Spectrum Clock Generators (SSCGs) with the PPC405GP, visit the technical
documents area of the AMCC PowerPC web site.
Specifications” on page 47. Further requirements are detailed in the Clocking chapter of the PowerPC 405GP Embedded Processor
User’s Manual.
three-state buffers instead of strapping resistors, and minimizing trace lengths and stubs.
3
Function
2, 3
2
PPC405GP Peripheral Attach
Internal Arbiter Disabled
Synchronous PCI Mode
Internal Arbiter Enabled
PPC405GP PCI Attach
Asynchronous Mode
(Part 2 of 2)
16-bit ROM
32-bit ROM
Divide by 1
Divide by 2
Divide by 3
Divide by 4
Divide by 2
Divide by 3
Divide by 4
Divide by 5
8-bit ROM
Reserved
Option
GPIO4[TS2O]
GPIO1[TS1E]
AF18/AB18
UART1_Tx
EMCTxErr
D18/A20
K25/K20
HoldAck
AC2/N3
ExtAck
Revision 2.03 – September 7, 2007
U2/P4
Y3/U4
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
Ball Strapping
Data Sheet
GPIO2[TS2E]
UART1_RTS/
UART1_DTR
EMCTxEn
C20/C19
K23/J21
AD2/N7
0
1
0
1
0
1
0
1
0
1
0
1
AMCC