PPC405GP-3BE133C AMCC [Applied Micro Circuits Corporation], PPC405GP-3BE133C Datasheet - Page 33

• Manufacturer Part Number: PPC405GP-3BE133C
• Description: Power PC 405GP Embedded Processor
• Manufacturer: AMCC [Applied Micro Circuits Corporation]

Revision 2.03 – September 7, 2007
Signal List
The following table provides a summary of the number of package pins associated with each functional interface
group.
Multiplexed Pins
In the table “Signal Functional Description” on page 35, each external signal is listed along with a description of the
signal function. Some signals are multiplexed on the same pin (ball) so that the pin can be used for different
functions. Multiplexed signals are shown as a default signal with a secondary signal in square brackets (for
example, GPIO1[TS1E]). Active-low signals (for example, RAS) are marked with an overline.
It is expected that in any single application a particular pin will always be programmed to serve the same function.
The flexibility of multiplexing allows a single chip to offer a richer pin selection than would otherwise be possible.
In addition to multiplexing, many pins are also multi-purpose. For example, the EBC peripheral controller address
pins are used as outputs by the PPC405GP to broadcast an address to external slave devices when the
PPC405GP has control of the external bus. When, during the course of normal chip operation, an external master
gains ownership of the external bus, these same pins are used as inputs which are driven by the external master
and received by the EBC in the PPC405GP. In this example, the pins are also bidirectional, serving as both inputs
and outputs.
Intialization Strapping
One group of pins is used as strapped inputs during system reset. These pins function as strapped inputs only
during reset and are used for other functions during normal operation (see “Strapping” on page 55). Note that the
use of these pins for strapping is not considered multiplexing since the strapping function is not programmable.
AMCC
Data Sheet
Pin Summary
Thermal (and Gnd)
External peripheral
Internal peripheral
Total Signal Pins
External master
Total Pins
Interrupts
Reserved
Ethernet
SDRAM
Group
System
JTAG
OV
V
Gnd
PCI
DD
DD
413-Ball package
25 mm
300
413
60
18
71
96
15
19
38
22
26
15
12
9
7
5
405GP – Power PC 405GP Embedded Processor
No. of Pins
35 mm
300
456
60
18
71
96
15
19
32
24
60
36
9
7
5
4
456-Ball Package
27mm
300
456
60
18
71
96
15
19
24
24
56
36
16
9
7
5
33