HFDOM44KR016 HANBIT [Hanbit Electronics Co.,Ltd], HFDOM44KR016 Datasheet - Page 12

• Manufacturer Part Number: HFDOM44KR016
• Description: 40Pin Flash Disk Module Min.8MB ~ Max.1GB, True IDE Interface Mode, 3.3V / 5.0V Operating
• Manufacturer: HANBIT [Hanbit Electronics Co.,Ltd]

HANBit
URL:www.hbe.co.kr
Rev. 1.0 (December, 2004)
accept a command.
Bit 5 (DWF): This bit, if set, indicates a write fault has occurred.
Bit 4 (DSC): This bit is set when the CompactFlash Storage Card is ready.
Bit 3 (DRQ): The Data Request is set when the CompactFlash Storage Card requires the
information to be transferred either to or from the host through the Data register.
Bit 2 (CORR): This bit is set when a Correctable data error has been encountered and the data has been corrected.
This condition does not terminate a multi-sector read operation.
Bit 1 (IDX): This bit is always set to 0.
Bit 0 (ERR): This bit is set when the previous command has ended in some type of error. The bits in the Error
register contain additional information describing the error. It is recommended
that media access commands (such as Read Sectors and Write Sectors) that end with an
error condition should have the address of the first sector in error in the command block
registers.
9) Device Control Register( Address – 3F6h[376h]; Offset Eh)
This register is used to control the CompactFlash Storage Card interrupt request and to issue an ATA soft reset to
the card. This register can be written even if the device is BUSY. The bits are defined as follows:
Bit 7: this bit is an X (don’t care).
Bit 6: this bit is an X (don’t care).
Bit 5: this bit is an X (don’t care).
Bit 4: this bit is an X (don’t care).
Bit 3: this bit is ignored by the CompactFlash Storage Card.
Bit 2 (SW Rst): this bit is set to 1 in order to force the CompactFlash Storage Card to perform an AT Disk
controller Soft Reset operation. This does not change the PCMCIA Card
Configuration Registers (4.3.2 to 4.3.5) as a hardware Reset does. The Card remains in
Reset until this bit is reset to ‘0.’
Bit 1 (-IEn): the Interrupt Enable bit enables interrupts when the bit is 0. When the bit is 1,
The interrupts from the CompactFlash Storage Card are disabled. This bit also controls the Int bit in the
Configuration and Status Register. This bit is set to 0 at power on and Reset.
Bit 0: this bit is ignored by the CompactFlash Storage Card.
10) Card (Drive) Address Register(Address 3F7h[377h]; Offset Fh)
This register is provided for compatibility with the AT disk drive interface. It is recommended that this register not
be mapped into the host’s I/O space because of potential conflicts on Bit 7. The bits are defined as follows:
Bit 7: this bit is in High Imoedence..
Implementation Note:
Conflicts may occur on the host data bus when this bit is provided by a Floppy Disk Controller
operating at the same addresses as the CompactFlash Storage Card. Following are some
possible solutions to this problem for the PCMCIA implementation:
1) Locate the CompactFlash Storage Card at a non-conflicting address, i.e. Secondary
address (377) or in an independently decoded Address Space when a Floppy Disk Controller
is located at the Primary addresses.
2) Do not install a Floppy and a CompactFlash Storage Card in the system at the same time.
3) Implement a socket adapter, which can be programmed to (conditionally) tri-state D7 of I/0
address 3F7h/377h when a Compact Flash Storage Card is installed and conversely to tri-state
D6-D0 of I/O address 3F7h/377h when a floppy controller is installed.
4) Do not use the CompactFlash Storage Card’s Drive Address register. This may be
D&
D7
X
X
-WTG
D6
D6
X
-HS3
D5
D5
X
Card (Drive) Address Register
Device Control Register
-HS2
D4
D4
X
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-HS1
D3
D3
1
SW Rst
-HS0
D2
D2
HFDOM44KRxxx
-nDS1
-IEn
D1
D1
HANBit Electronics Co., Ltd.
-nDS0
D0
D0
0