GS882Z18BB-150I GSI [GSI Technology], GS882Z18BB-150I Datasheet
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GS882Z18BB-150I
Manufacturer Part Number
GS882Z18BB-150I
Description
9Mb Pipelined and Flow Through Synchronous NBT SRAM
Manufacturer
GSI [GSI Technology]
Datasheet
1.GS882Z18BB-150I.pdf
(34 pages)
119-bump and 165-bump BGA
Commercial Temp
Industrial Temp
Features
• NBT (No Bus Turn Around) functionality allows zero wait
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• User-configurable Pipeline and Flow Through mode
• ZQ mode pin for user-selectable high/low output drive
• IEEE 1149.1 JTAG-compatible Boundary Scan
• On-chip parity encoding and error detection
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 2M, 4M, and 18M devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• JEDEC-standard 119-bump BGA and 165-bump FPBGA
Rev: 1.02 10/2004
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Read-Write-Read bus utilization; fully pin-compatible with
both pipelined and flow through NtRAM™, NoBL™ and
ZBT™ SRAMs
packages
Flow Through
Pipeline
3-1-1-1
2-1-1-1
Curr (x32/x36)
Curr (x32/x36)
Curr (x18)
Curr (x18)
tCycle
tCycle
t
t
KQ
KQ
9Mb Pipelined and Flow Through
Synchronous NBT SRAM
Paramter Synopsis
1/34
-333
250
290
200
230
2.5
3.0
4.5
4.5
-300
Functional Description
The GS882Z18/36B is a 9Mbit Synchronous Static SRAM.
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other
pipelined read/double late write or flow through read/single
late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS882Z18/36B may be configured by the user to operate
in Pipeline or Flow Through mode. Operating as a pipelined
synchronous device, in addition to the rising-edge-triggered
registers that capture input signals, the device incorporates a
rising edge triggered output register. For read cycles, pipelined
SRAM output data is temporarily stored by the edge-triggered
output register during the access cycle and then released to the
output drivers at the next rising edge of clock.
The GS882Z18/36B is implemented with GSI's high
performance CMOS technology and is available in JEDEC-
standard 119-bump BGA and 165-bump FPBGA packages.
230
265
185
210
2.5
3.3
5.0
5.0
-250
200
230
160
185
2.5
4.0
5.5
5.5
GS882Z18/36BB/D-333/300/250/200/150
-200
170
195
140
160
3.0
5.0
6.5
6.5
-150
140
160
128
145
3.8
6.7
7.5
7.5
Unit
mA
mA
mA
mA
ns
ns
ns
ns
© 2001, GSI Technology
333 MHz–150 MHz
2.5 V or 3.3 V V
2.5 V or 3.3 V I/O
DD