GS8644V72C-250I GSI [GSI Technology], GS8644V72C-250I Datasheet - Page 31

• Manufacturer Part Number: GS8644V72C-250I
• Description: 4M x 18, 2M x 36, 1M x 72 72Mb S/DCD Sync Burst SRAMs
• Manufacturer: GSI [GSI Technology]

JTAG Port AC Test Conditions
Notes:
1.
2.
JTAG TAP Instruction Set Summary
Rev: 1.03 11/2004
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Notes:
1.
2.
Instruction
SAMPLE-Z
Include scope and jig capacitance.
Test conditions as as shown unless otherwise noted.
PRELOAD
Instruction codes expressed in binary, MSB on left, LSB on right.
Default instruction automatically loaded at power-up and in test-logic-reset state.
SAMPLE/
IDCODE
BYPASS
EXTEST
Output reference level
RFU
RFU
GSI
Input reference level
Input high level
Input slew rate
Input low level
Parameter
Code
000
001
010
011
100
101
110
111
Places the Boundary Scan Register between TDI and TDO.
Preloads ID Register and places it between TDI and TDO.
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
Forces all RAM output drivers to High-Z.
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
GSI private instruction.
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
Places Bypass Register between TDI and TDO.
Conditions
V
DD
V
V
1 V/ns
0.2 V
DDQ
DDQ
– 0.2 V
/2
/2
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GS8644V18(B/E)/GS8644V36(B/E)/GS8644V72(C)
Description
DQ
* Distributed Test Jig Capacitance
JTAG Port AC Test Load
V
DDQ
/2
Product Preview
50Ω
© 2003, GSI Technology
30pF
Notes
1, 2
1
1
1
1
1
1
1
*