GS880E18BGT-150I GSI [GSI Technology], GS880E18BGT-150I Datasheet - Page 10
![no-image](/images/no-image-200.jpg)
GS880E18BGT-150I
Manufacturer Part Number
GS880E18BGT-150I
Description
512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs
Manufacturer
GSI [GSI Technology]
Datasheet
1.GS880E18BGT-150I.pdf
(28 pages)
- Current page: 10 of 28
- Download datasheet (646Kb)
Notes:
1.
2.
3.
Rev: 1.02 10/2004
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.
The upper portion of the diagram assumes active use of only the Enable (E1, E2, and E3) and Write (B
control inputs, and that ADSP is tied high and ADSC is tied low.
The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and
assumes ADSP is tied high and ADV is tied low.
X
CW
X
First Write
Burst Write
W
W
Simplified State Diagram
CW
10/28
W
CR
R
CR
R
Deselect
X
GS880E18/32/36BT-333/300/250/200/150
R
CR
First Read
Burst Read
R
R
CR
A
X
, B
X
B
, B
C
, B
© 2001, GSI Technology
D
, BW, and GW)
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